Patents by Inventor Hideo Inaba
Hideo Inaba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7017541Abstract: A driving cam includes a circular surface portion at an outer cam surface thereof. When an engine is turned off, the circular surface portion is brought into contact with a roller. Thereby, even if a load is applied to the control axis member, no rotational force is circumferentially applied to the driving cam. As the result, even if a driving force is not applied from a motor to the driving cam, a rotational angle of the driving cam and an axial position of the control axis member are kept constant. Therefore, it is possible to keep the driving cam and the control axis member at a constant position without adding a complicated mechanism.Type: GrantFiled: November 12, 2004Date of Patent: March 28, 2006Assignee: Denso CorporationInventors: Hideo Inaba, Akira Shibata
-
Patent number: 7006401Abstract: Refresh of memory cells is performed periodically by a refresh timer, and collision between memory access and memory refresh is avoided. When memory access occurs, an F/F 163 is set by a one shot pulse from an OS circuit 161, a memory access request is inputted to a memory accessing pulse generator circuit 171 through a NOR gate 167, and a latch control signal LC and an enable signal REN are outputted. When a refresh request from the refresh timer is inputted to an AND gate 168 during the memory access, the output of the NOR gate 167 is at the “L” level, and the refresh request is blocked by the AND gate 168. Thereafter, at the time when the latch control signal LC is turned into the “L” level, F/Fs 163, 164 and 165 are reset, the output of the NOR gate 167 is turned into the “H” level, the refresh request is inputted to a refreshing pulse generator circuit 170, and a refresh enable signal RERF is outputted.Type: GrantFiled: December 25, 2002Date of Patent: February 28, 2006Assignee: NEC Electronics Corp.Inventors: Hiroyuki Takahashi, Takuya Hirota, Noriaki Komatsu, Atsushi Nakagawa, Susumu Takano, Masahiro Yoshida, Yuuji Torige, Hideo Inaba
-
Publication number: 20060000433Abstract: An actuator for a valve lift control device linearly moves a control shaft to change a valve lift in accordance with an axial position of the control shaft. A first and a second rotation cam integrally rotate around a common rotation axis by transmission of torque, so that a direct acting follower, which includes a first and a contact members, linearly moves with a control shaft. The first and a second rotation cams are respectively in contact with the first and the second contact members via a first and a second contact points. The first contact point is located on the opposite side of the second contact point with respect to the rotation axis. A sum of a first rotation cam lift of the first rotation cam and a second rotation cam lift of the second rotation cam is substantially constant in a predetermined rotation angular range of the first rotation cam and the second rotation cam.Type: ApplicationFiled: June 21, 2005Publication date: January 5, 2006Applicant: DENSO CORPORATIONInventors: Yasuyoshi Suzuki, Akihiko Kameshima, Hideo Inaba, Jouji Yamaguchi
-
Publication number: 20050207214Abstract: A semiconductor memory device is provided which effectively reduces a consumption of current of a system of circuits associated with refresh operations. A control signal circuit 2 controls n-channel transistors 3C, 4B to be in an OFF-state based on an internal chip select signal SCI in an interval time period between the refresh operations, wherein the n-channel transistors 3C, 4B are connected between the system of circuits associated with refresh operations (an internal voltage-down circuit 3 and a boost circuit 4) and the ground, so as to break down a leak path of the system of circuits associated with refresh operations for reducing the leakage of current. At a timing of starting the refresh operation by triggering a timer, the internal chip select signal SCI is transitioned to a high level for supplying a ground voltage to the internal voltage-down circuit 3 and the boost circuit 4.Type: ApplicationFiled: May 16, 2005Publication date: September 22, 2005Inventors: Hiroyuki Takahashi, Atsushi Nakagawa, Hideo Inaba
-
Publication number: 20050207252Abstract: A test method and a test circuit which enable operations to be checked when the time interval between a refresh operation and a read or write operation is forcibly reduced. Timings for a read or write operation in a normal operation mode and in a test mode are determined on the basis of an address transition detection circuit. A timing for a refresh operation in the normal operation mode is set on the basis of a normal refreshing pulse signal generated by a refresh pulse generating circuit in response to a timing signal generated by a timer circuit. A timing for a refresh operation in the test mode is set on the basis of a first testing refresh pulse generation signal generated by a first testing refresh pulse generating circuit in response to the address transition detection signal.Type: ApplicationFiled: December 10, 2002Publication date: September 22, 2005Inventors: Hiroyuki Takahashi, Hideo Inaba, Syouzou Uchida
-
Patent number: 6947345Abstract: A semiconductor memory device is provided, which is capable of effectively reducing a current comsumption caused by a self-refresh operation in a stand-by mode. In the refresh operation in the stand-by mode, under the control by a refresh control circuit 8B, firstly, a suppression is made for current driving abilities of sense amplifiers 70A˜70D provided for amplifying data signals appearing on bit lines, and secondly, an expansion is made of a pulse width of a row enable signal RE, which defines a period of time for selecting word lines WL, and thirdly, parallel activations of plural word lines are made based on the row enable signal RE with the expanded pulse width, thereby reducing the frequency of operations of the circuit system associated with the refresh operations, resulting in a suppression of the current consumption.Type: GrantFiled: March 28, 2002Date of Patent: September 20, 2005Assignee: NEC Electronics CorporationInventors: Hiroyuki Takahashi, Hideo Inaba, Atsushi Nakagawa
-
Patent number: 6944081Abstract: A semiconductor memory device capable of a further reduction in power consumption for refresh operation is provided. Cell arrays S0, S1 are divided into respective four blocks B0˜B3 and B10˜B13. In a normal read/write operation, by address data designating a word line, one of the cell arrays is selected, and also one block is selected in the selected cell array, and further one word line is selected in the selected block. In a refresh operation, one of the cell arrays is selected, and four blocks in the selected cell array are simultaneously refreshed. Namely, respective one word line is selected from each of the four blocks, and the selected word lines are refreshed, thereby to reduce a power comsumption as compared to when the plural cell arrays are refreshed.Type: GrantFiled: August 30, 2001Date of Patent: September 13, 2005Assignee: NEC Electronics CorporationInventors: Hiroyuki Takahashi, Atsushi Nakagawa, Yoshiyuki Katou, Hideo Inaba, Noriaki Komatsu, Takuya Hirota, Masahiro Yoshida
-
Patent number: 6941763Abstract: This heat pump and dehumidifying apparatus have small energy-consumed per moisture-removed ratios. Their components include a pressurizer for raising refrigerant pressure; a condenser for condensing refrigerant, thereby heating a high-temperature heat source fluid; an evaporator for evaporating refrigerant to cool a low-temperature heat source fluid; and a heat exchanger in a refrigerant path connecting the condenser and the evaporator for evaporating and condensing refrigerant under an intermediate pressure between the condensor pressure and the evaporator pressure. The low-temperature heat source fluid is successively cooled by the heat exchanger, cooled by the evaporator, and heated by the heat exchanger. This fluid can be precooled by the heat exchanger before cooling in the evaporator, and heat removed during precooling can be returned to the fluid after cooling by the evaporator.Type: GrantFiled: November 12, 2003Date of Patent: September 13, 2005Assignee: Ebara CorporationInventors: Kensaku Maeda, Hideo Inaba, Shunro Nishiwaki
-
Patent number: 6928020Abstract: A semiconductor memory device is provided which operates according to the specification of an SRAM, and which is capable of making the memory cycle shorter than heretofore, without normal access being delayed by the influence of refresh. An ATD circuit (4) receives change of an address (“Address”), and generates a one shot pulse in an address transition detect signal (ATD) after an address skew period has elapsed. In the case of a write request, a write enable signal (/WE) is dropped within the address skew period. First, writing or reading is performed from the rising edge of the one shot pulse, and, in the case of writing, late writing is performed using the address and the data which were presented at the time of the directly preceding write request. Next, refresh is performed during the period from the falling edge of the one shot pulse until the address skew period of the subsequent memory cycle is completed.Type: GrantFiled: June 2, 2004Date of Patent: August 9, 2005Assignee: NEC Electronics CorporationInventors: Hiroyuki Takahashi, Hideo Inaba, Atsushi Nakagawa
-
Patent number: 6922371Abstract: A semiconductor memory device is provided which effectively reduces a consumption of current of a system of circuits associated with refresh operations. A control signal circuit 2 controls n-channel transistors 3C, 4B to be in an OFF-state based on an internal chip select signal SCI in an interval time period between the refresh operations, wherein the n-channel transistors 3C, 4B are connected between the system of circuits associated with refresh operations (an internal voltage-down circuit 3 and a boost circuit 4) and the ground, so as to break down a leak path of the system of circuits associated with refresh operations for reducing the leakage of current. At a timing of starting the refresh operation by triggering a timer, the internal chip select signal SCI is transitioned to a high level for supplying a ground voltage to the internal voltage-down circuit 3 and the boost circuit 4.Type: GrantFiled: May 28, 2002Date of Patent: July 26, 2005Assignee: NEC Electronics CorporationInventors: Hiroyuki Takahashi, Atsushi Nakagawa, Hideo Inaba
-
Publication number: 20050120987Abstract: A driving cam includes a circular surface portion at an outer cam surface thereof. When an engine is turned off, the circular surface portion is brought into contact with a roller. Thereby, even if a load is applied to the control axis member, no rotational force is circumferentially applied to the driving cam. As the result, even if a driving force is not applied from a motor to the driving cam, a rotational angle of the driving cam and an axial position of the control axis member are kept constant. Therefore, it is possible to keep the driving cam and the control axis member at a constant position without adding a complicated mechanism.Type: ApplicationFiled: November 12, 2004Publication date: June 9, 2005Applicant: DENSO CORPORATIONInventors: Hideo Inaba, Akira Shibata
-
Patent number: 6876592Abstract: A semiconductor memory device capable of accelerating address access and shortening cycle time is provided. A first address decoder (2) and first refresh address decoder (5) respectively decode an external address (Xn) supplied from outside the semiconductor memory device and a refresh address (RXn) used for refreshing within the semiconductor memory device. A multiplexer (8) selects the external address side decode signal (XnDm) or the refresh address side decode signal (XnRm) and outputs the signal as a decode signal (XnMm) based on an external address transmission signal (EXTR) and refresh address transmission signal (RFTR) so that a refresh operation and a read/write operation is performed continuously within one memory cycle. A word driver (10) then decodes decode signals (XnMm, XpMq) selected with multiplexer (8) and so forth, and activates a word line (WLmq).Type: GrantFiled: March 7, 2001Date of Patent: April 5, 2005Assignee: NEC Electronics CorporationInventors: Hiroyuki Takahashi, Hideo Inaba, Masatoshi Sonoda, Yoshiyuki Kato, Atsushi Nakagawa
-
Publication number: 20050047239Abstract: Refresh of memory cells is performed periodically by a refresh timer, and collision between memory access and memory refresh is avoided. When memory access occurs, an F/F 163 is set by a one shot pulse from an OS circuit 161, a memory access request is inputted to a memory accessing pulse generator circuit 171 through a NOR gate 167, and a latch control signal LC and an enable signal REN are outputted. When a refresh request from the refresh timer is inputted to an AND gate 168 during the memory access, the output of the NOR gate 167 is at the “L” level, and the refresh request is blocked by the AND gate 168. Thereafter, at the time when the latch control signal LC is turned into the “L” level, F/Fs 163, 164 and 165 are reset, the output of the NOR gate 167 is turned into the “H” level, the refresh request is inputted to a refreshing pulse generator circuit 170, and a refresh enable signal RERF is outputted.Type: ApplicationFiled: December 25, 2002Publication date: March 3, 2005Inventors: Hiroyuki Takahashi, Takuya Hirota, Noriaki Komatsu, Atsushi Nakagawa, Susumu Takano, Masahiro Yoshida, Yuuji Torige, Hideo Inaba
-
Patent number: 6834020Abstract: A semiconductor memory device is provided which operates according to the specification of an SRAM, and which is capable of making the memory cycle shorter than heretofore, without normal access being delayed by the influence of refresh. An ATD circuit (4) receives change of an address (“Address”), and generates a one shot pulse in an address transition detect signal (ATD) after an address skew period has elapsed. In the case of a write request, a write enable signal (/WE) is dropped within the address skew period. First, writing or reading is performed from the rising edge of the one shot pulse, and, in the case of writing, late writing is performed using the address and the data which were presented at the time of the directly preceding write request. Next, refresh is performed during the period from the falling edge of the one shot pulse until the address skew period of the subsequent memory cycle is completed.Type: GrantFiled: October 9, 2002Date of Patent: December 21, 2004Assignee: NEC Electronics CorporationInventors: Hiroyuki Takahashi, Hideo Inaba, Atsushi Nakagawa
-
Publication number: 20040232451Abstract: A semiconductor memory device is provided which effectively reduces a consumption of current of a system of circuits associated with refresh operations. A control signal circuit 2 controls n-channel transistors 3C, 4B to be in an OFF-state based on an internal chip select signal SCI in an interval time period between the refresh operations, wherein the n-channel transistors 3C, 4B are connected between the system of circuits associated with refresh operations (an internal voltage-down circuit 3 and a boost circuit 4) and the ground, so as to break down a leak path of the system of circuits associated with refresh operations for reducing the leakage of current. At a timing of starting the refresh operation by triggering a timer, the internal chip select signal SCI is transitioned to a high level for supplying a ground voltage to the internal voltage-down circuit 3 and the boost circuit 4.Type: ApplicationFiled: December 5, 2003Publication date: November 25, 2004Inventors: Hiroyuki Takahashi, Atsushi Nakagawa, Hideo Inaba
-
Publication number: 20040218435Abstract: A semiconductor memory device is provided which operates according to the specification of an SRAM, and which is capable of making the memory cycle shorter than heretofore, without normal access being delayed by the influence of refresh. An ATD circuit (4) receives change of an address (“Address”), and generates a one shot pulse in an address transition detect signal (ATD) after an address skew period has elapsed. In the case of a write request, a write enable signal (/WE) is dropped within the address skew period. First, writing or reading is performed from the rising edge of the one shot pulse, and, in the case of writing, late writing is performed using the address and the data which were presented at the time of the directly preceding write request. Next, refresh is performed during the period from the falling edge of the one shot pulse until the address skew period of the subsequent memory cycle is completed.Type: ApplicationFiled: June 2, 2004Publication date: November 4, 2004Inventors: Hiroyuki Takahashi, Hideo Inaba, Atsushi Nakagawa
-
Publication number: 20040194478Abstract: This heat pump and dehumidifying apparatus have small energy-consumed per moisture-removed ratios. Their components include a pressurizer for raising refrigerant pressure; a condenser for condensing refrigerant, thereby heating a high-temperature heat source fluid; an evaporator for evaporating refrigerant to cool a low-temperature heat source fluid; and a heat exchanger in a refrigerant path connecting the condenser and the evaporator for evaporating and condensing refrigerant under an intermediate pressure between the condensor pressure and the evaporator pressure. The low-temperature heat source fluid is successively cooled by the heat exchanger, cooled by the evaporator, and heated by the heat exchanger. This fluid can be precooled by the heat exchanger before cooling in the evaporator, and heat removed during precooling can be returned to the fluid after cooling by the evaporator.Type: ApplicationFiled: November 12, 2003Publication date: October 7, 2004Inventors: Kensaku Maeda, Hideo Inaba, Shunro Nishiwaki
-
Publication number: 20040170081Abstract: The present invention provides a non-synchronous semiconductor memory device configured as a pseudo-SRAM and capable of relaxing the limitation to address skew and improving the read rate. A data latch circuit 110 holds data having been read out of memory cells in a memory cell array 106 designated by a tow address included in an address ADD in a read mode. Upon transitions of column addresses A0, A1 included in the address, a multiplexer 111 sequentially and non-synchronously feeds out the data held in the data latch circuit 110 based on the column addresses A0, A1.Type: ApplicationFiled: April 26, 2004Publication date: September 2, 2004Inventors: Hiroyuki Takahashi, Hideo Inaba, Atsushi Nakagawa
-
Publication number: 20040158671Abstract: A semiconductor memory device is provided for preventing a late-write from disturbing a refresh operation and also for reducing a current consumption in a write cycle with execution of the late-write. Upon a transition of an address ADD, an address transition detector circuit 101 detects this address transition. Upon receipt of a result of detection by the address transition detector circuit 101, a state control circuit 102 judges an operation to be executed, from an output enable signal /OE and a write enable signal /WE, and then outputs any of a read statement RS, a write statement WS, and a refresh statement FS. According to a clock signal ACLK, input signals such as addresses are taken for executions of operations based on the statements.Type: ApplicationFiled: December 4, 2003Publication date: August 12, 2004Inventors: Hiroyuki Takahashi, Atsushi Nakagawa, Hideo Inaba
-
Publication number: 20040130958Abstract: A semiconductor memory device is provided, which is capable of effectively reducing a current comsumption caused by a self-refresh operation in a stand-by mode.Type: ApplicationFiled: February 17, 2004Publication date: July 8, 2004Inventors: Hiroyuki Takahashi, Hideo Inaba, Atsushi Nakagawa