Abstract: A dehumidifying air-conditioning apparatus comprises a pressurizer (4) for raising a pressure of a refrigerant, a condenser (5) for condensing the refrigerant to heat a high-temperature heat source fluid, and an evaporator (1) for evaporating the refrigerant to cool process air to a temperature lower than its dew point. The dehumidifying air-conditioning apparatus further comprises a refrigerant path branched into a plurality of branched refrigerant paths (42, 43, 44) between the condenser (5) and the evaporator (1). A first heat exchanging portion (21) is disposed in the branched refrigerant path for evaporating the refrigerant under an intermediate pressure between the condensing pressure of the condenser (5) and the evaporating pressure of the evaporator (1) to cool the process air by evaporation of the refrigerant under the intermediate pressure.

Abstract: A semiconductor memory device capable of accelerating address access and shortening cycle time is provided. A first address decoder (2) and first refresh address decoder (5) respectively decode an external address (Xn) supplied from outside the semiconductor memory device and a refresh address (RXn) used for refreshing within the semiconductor memory device. A multiplexer (8) selects the external address side decode signal (XnDm) or the refresh address side decode signal (XnRm) and outputs the signal as a decode signal (XnMm) based on an external address transmission signal (EXTR) and refresh address transmission signal (RFTR) so that a refresh operation and a read/write operation is performed continuously within one memory cycle. A word driver (10) then decodes decode signals (XnMm, XpMq) selected with multiplexer (8) and so forth, and activates a word line (WLmq).

Abstract: A semiconductor storage having the same memory cells as a DRAM, operating in SRAM specifications, and having advantages such as a small chop size, a low power consumption, a low manufacturing cost, no access delay due to skew, and no memory cell breakdown. An ATD circuit (3) generates a one-shot pulse added to an address change detection signal (ATD) from a change of the address (Address) supplied from external. By combining one-shot pulse produced for each bit of the address, only one one-shot pulse is generated even if the address includes skew. A memory cell is refreshed by using a refresh address (R_ADD) generated by a refresh control circuit (4) during the time when a one-shot pulse is generated. At the fall of the one-shot pulse, a latch control signal (LC) is generated, and the address is taken in a latch (2) so as to access a memory cell array (6).

Abstract: A semiconductor memory device capable of a further reduction in power consumption for refresh operation is provided. Cell arrays S0, S1 are divided into respective four blocks B0˜B3 and B10˜B13. In a normal read/write operation, by address data designating a word line, one of the cell arrays is selected, and also one block is selected in the selected cell array, and further one word line is selected in the selected block. In a refresh operation, one of the cell arrays is selected, and four blocks in the selected cell array are simultaneously refreshed. Namely, respective one word line is selected from each of the four blocks, and the selected word lines are refreshed, thereby to reduce a power comsumption as compared to when the plural cell arrays are refreshed.

Abstract: The present invention provides a semiconductor memory device capable of checking operation in the worst case in address combinations, and its manufacturing method. Specific data for test are written into a memory cell array 30. Then, a test signal TE1 is set “1” to set a device in a test mode. Refresh addresses for test are then stored in a data store circuit 51. A first address for test is applied to an address terminal 21, whereby a normal read or write operation is accomplished based on the first address for test. A second address for test is applied to the address terminal 21, whereby a refresh operation is accomplished based on the address for test, and subsequently another normal read or write operation is accomplished based on the second address for test. Data of the memory cell array 30 are checked to decide the presence or absence of any abnormality.

Abstract: A heat pump with a high coefficient of performance and a dehumidifying apparatus consumes a small amount of energy per amount of moisture removal. The heat pump includes a pressurizer for raising a pressure of a refrigerant; a condenser for condensing the refrigerant to heat a high-temperature heat source fluid; an evaporator for evaporating the refrigerant to cool a low-temperature heat source fluid; and heat exchanger disposed in a refrigerant path connecting the condenser and the evaporator for evaporating and condensing the refrigerant under an intermediate pressure between the condensing pressure of the condenser and the evaporating pressure of the evaporator 210. The low-temperature heat source fluid is successively cooled by the heat exchanging means, cooled by the evaporator, and heated by the heat exchanger in such order.

Abstract: A one-shot signal generation circuit is provided which makes it easy to adjust pulse width and to deal with variation of skew of an ATD signal, and can reduce chip area. A timing determination section (100) is reset by an edge of a first detected signal among a plurality of address transition detection signals (ATD signals) which have arrived within the skew period of an address signal, measures a first predetermined time by taking an edge of a second detected signal as start instant, and outputs a signal DST which reflects the result of this measurement. A timing determination section (110) measures a second predetermined time by taking an edge of the first detected signal as start instant, and outputs a signal PG which reflects the result of this measurement. An LC generation circuit (14) outputs a one-shot signal (LC) whose start instant is determined by the signal PG and whose end instant is determined by the signal DST.

Abstract: A one-shot signal generation circuit is provided which makes it easy to adjust pulse width and to deal with variation of skew of an ATD signal, and can reduce chip area. A timing determination section (100) is reset by an edge of a first detected signal among a plurality of address transition detection signals (ATD signals) which have arrived within the skew period of an address signal, measures a first predetermined time by taking an edge of a second detected signal as start instant, and outputs a signal DST which reflects the result of this measurement. A timing determination section (110) measures a second predetermined time by taking an edge of the first detected signal as start instant, and outputs a signal PG which reflects the result of this measurement. An LC generation circuit (14) outputs a one-shot signal (LC) whose start instant is determined by the signal PG and whose end instant is determined by the signal DST.

Abstract: A semiconductor memory device is provided which operates according to the specification of an SRAM, and which is capable of making the memory cycle shorter than heretofore, without normal access being delayed by the influence of refresh. An ATD circuit (4) receives change of an address (“Address”), and generates a one shot pulse in an address transition detect signal (ATD) after an address skew period has elapsed. In the case of a write request, a write enable signal (/WE) is dropped within the address skew period. First, writing or reading is performed from the rising edge of the one shot pulse, and, in the case of writing, late writing is performed using the address and the data which were presented at the time of the directly preceding write request. Next, refresh is performed during the period from the falling edge of the one shot pulse until the address skew period of the subsequent memory cycle is completed.

Abstract: The invention provides a semiconductor memory device incorporating memory cells the same as for DRAM and which operates under SRAM specification, where the chip size is small and power consumption and cost are low, and for which access delay or memory cell data destruction due to skew incorporated in an address does not arise. An ATD circuit (3) generates a one shot pulse for an address transition detection signal (ATD) from transition of an externally supplied address (Address). At this time, by generating the one shot pulse for each bit of the address and then combining these, then even in the case where the address contains a skew, the one shot pulse is only generated once. At first, refresh is performed during the generation period of the one shot pulse, using a refresh address (R_ADD) generated by a refresh control circuit (4). Then, on receipt of a fall in the one shot pulse, a latch control signal (LC) is generated, the address is latched by the latch (2) and the memory cell array (6) accessed.

Abstract: A compact and energy efficient air conditioning system is operated with a desiccant material having a high differential adsorption capacity even at lower regeneration temperatures than those in the conventional system. The desiccant assisted air conditioning system comprises a process air path (A) for flowing process air to adsorb moisture from the process air by a desiccant member, and a regeneration air path (B) for flowing regeneration air heated by a heat source to desorb moisture from the desiccant member (103). The desiccant member is arranged so that the process air or the regeneration air flows alternatingly through the desiccant member. The desiccant member is arranged so that the process air or the regeneration air flows alternatingly through the desiccant member.

Abstract: It is an object of the present invention to provide a dehumidifying air-conditioning system which increases the entire energy efficiency thereof to have a low operating cost, consume reduced electric energy in daytime, and radiate minimum heat into the atmosphere in thermal storage operation at night.

Abstract: A semiconductor memory device has a ring oscillator that is configured so that its period in the time before reaching a raised voltage is made short and further so that its period after reaching the raised voltage is made long, and a voltage boosting circuit that raises the voltage on a word line of memory cells, based on a boosted potential that is output from the ring oscillator. The ring oscillator performs a plurality of voltage boosting operations until the boosted potential of the word line of the memory cells reaches the voltage that is required for writing of data thereinto, and makes the period of the ring oscillator output ROC short while performing the plurality of boosting operations, and makes the period of the ring oscillator output ROC long after a prescribed raised voltage level is reached, thereby reducing the amount of AC current that flows in the ring oscillator itself.

Abstract: In a static type semiconductor memory device, a word decoder is connected to a plurality of word lines to decode an address signal to select one of the plurality of word lines. A resistor load type memory cell is connected to said selected word line. The resistor load type memory cell is composed of two pairs of a load resistor and a MOS transistor and the two pairs are connected to form a flip-flop. A word line voltage boosting circuit is connected to the word decoder to boost a voltage of the selected word line to a voltage higher than a power supply voltage in response to a boost control signal. A timer circuit includes a replica of the load transistor of one of the two pair and replicas of the MOS transistors of the two pair. The timer circuit generates the boost control signal for a predetermined time period in response to a start control signal to activate said word line voltage boosting circuit.

Abstract: In a level shifter, first and second integrated-circuit resistors are connected in series between a source voltage supplying terminal and the ground. The first and the second integrated-circuit have a common temperature characteristic and a common line width. A third integrated-circuit is connected to the first integrated-circuit resistor in parallel and-has another temperature characteristic. The first, the second, and the third integrated-circuit resistors form a voltage divider which divides a source voltage Vcc into a divided voltage. A differential amplifier has a noninverting terminal which is connected to a connection point between the first and the second integrated-circuit resistors, an output terminal, and a inverting terminal which is connected to the output terminal. The differential amplifier supplies the divided voltage to an integrated circuit as a level shifted voltage.

Abstract: An output circuit is incorporated in an integrated circuit for communicating with an external device, and includes a plurality of output inverting circuits. Each such inverting circuit is implemented by a series combination of a p-channel enhancement type field effect transistor and an n-channel enhancement type field effect transistor. The inverting circuits are coupled between a positive power voltage line and a ground voltage line electrically connected with a semiconductor substrate. The output circuit also includes a plurality of output pins, each coupled between an external load and one of the output inverting circuits, and a resistive element coupled between the ground voltage line and the semiconductor substrate, so that the ground voltage line hardly fluctuates in voltage level upon concurrent switching actions of the output inverting circuits.

Abstract: An ignition distributor has a hollow housing. A distributor cap having a caved portion that extends in the housing is mounted on one end of the housing. The other end of the housing supports a rotation shaft. An ignition coil is disposed in the caved portion of the distributor cap. A rotor electrode of a distributor section is connected to the shaft, and rotates around the caved portion of the distributor cap. Side electrodes are arranged to face the rotor electrode with its rotation. Thus, the space surrounding the ignition coil is fully utilized to arrange the distributor section. This results in a compact ignition distributor.

Abstract: A semiconductor integrated circuit provided with a monitor arrangement for evaluating functional transistors indirectly is disclosed. The monitor arrangement includes a plurality of monitor transistors having current paths connected in parallel between a pair of terminals and a selection circuit responsive to at least one external control signal for rendering one of the monitor transistors conductive.

Abstract: Thia-diazole derivatives having the following partial structural formula had selective herbicidal activity on some crops.