Patents by Inventor Hideto Sugawara

Hideto Sugawara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200058786
    Abstract: A semiconductor device includes a semiconductor body, first and second electrodes, and a control electrode. The semiconductor body includes first to fourth semiconductor layers. The first electrode is provided on a front surface of the semiconductor body. The second electrode is provided on a back surface of the semiconductor body. The control electrode is provided between the semiconductor body and the first electrode. The second semiconductor layer is positioned between a portion and other portion of the first semiconductor layer in a first direction directed along the front surface. The third semiconductor layer contacts the portion of first semiconductor layer and the second semiconductor layer. The third semiconductor layer includes a first end portion positioned in the portion of the first semiconductor layer and a second end portion positioned in the second semiconductor layer. The fourth semiconductor layer is selectively provided in the second end portion.
    Type: Application
    Filed: January 7, 2019
    Publication date: February 20, 2020
    Inventors: Hiroaki Yamashita, Syotaro Ono, Hisao Ichijo, Hideto Sugawara, Hiroshi Ohta
  • Patent number: 9312444
    Abstract: A semiconductor light emitting device includes a supporting substrate, a light emitting layer including a nitride semiconductor, and a nitride multilayer film. The nitride multilayer film includes a first layer including a first nitride semiconductor containing aluminum nitride, a second layer including a second nitride semiconductor containing gallium nitride, and a third layer including the first nitride semiconductor containing aluminum nitride.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: April 12, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideto Sugawara
  • Patent number: 8980664
    Abstract: According to one embodiment, a method for fabricating a stacked nitride-compound semiconductor structure includes forming a first protection film on a second surface of a substrate, forming a first nitride-compound semiconductor layer on the first surface of the substrate, forming a second protection film on the first nitride-compound semiconductor layer, removing the first protection film to expose the second surface of the substrate, forming a second nitride-compound semiconductor layer on the second surface of the substrate, and removing the second protection film to expose the first surface of the second nitride-compound semiconductor layer.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Kai, Hideto Sugawara
  • Patent number: 8796111
    Abstract: According to one embodiment, stacked layers of a nitride semiconductor include a substrate, a single crystal layer and a nitride semiconductor layer. The substrate does not include a nitride semiconductor and has a protrusion on a major surface. The single crystal layer is provided directly on the major surface of the substrate to cover the protrusion, and includes a crack therein. The nitride semiconductor layer is provided on the single crystal layer.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: August 5, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideto Sugawara, Masaaki Onomura
  • Publication number: 20140061660
    Abstract: A semiconductor light emitting device includes a supporting substrate, a light emitting layer including a nitride semiconductor, and a nitride multilayer film. The nitride multilayer film includes a first layer including a first nitride semiconductor containing aluminum nitride, a second layer including a second nitride semiconductor containing gallium nitride, and a third layer including the first nitride semiconductor containing aluminum nitride.
    Type: Application
    Filed: March 6, 2013
    Publication date: March 6, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hideto SUGAWARA
  • Publication number: 20130302931
    Abstract: According to one embodiment, stacked layers of a nitride semiconductor include a substrate, a single crystal layer and a nitride semiconductor layer. The substrate does not include a nitride semiconductor and has a protrusion on a major surface. The single crystal layer is provided directly on the major surface of the substrate to cover the protrusion, and includes a crack therein. The nitride semiconductor layer is provided on the single crystal layer.
    Type: Application
    Filed: July 19, 2013
    Publication date: November 14, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideto Sugawara, Masaaki Onomura
  • Patent number: 8541772
    Abstract: According to one embodiment, a nitride semiconductor stacked structure having a first surface includes a substrate, a first buffer layer, a first crystal layer, a second buffer layer and a second crystal layer. A step portion is provided in the substrate and includes an upper surface, a lower surface, and a side surface between the upper surface and the lower surface. The first buffer layer includes InsAltGa1-s-tN (0?s?0.05, 0?t?1) and covers the lower surface and the side surface. The first crystal layer is provided on the first buffer layer, includes InsAltGa1-s-tN (0?s?0.05, 0?t?0.05), and has an upper surface provided above the upper surface of the substrate. The second buffer layer includes InsAltGa1-s-tN (0?s?0.05, 0?t?1) and continuously covers the upper surface of the first crystal layer and the upper surface of the substrate. The second crystal layer covers the second buffer layer, includes InsAltGa1-s-tN (0?s?0.05, 0?t?0.05), and has the first surface.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: September 24, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideto Sugawara
  • Patent number: 8502350
    Abstract: According to one embodiment, stacked layers of a nitride semiconductor include a substrate, a single crystal layer and a nitride semiconductor layer. The substrate does not include a nitride semiconductor and has a protrusion on a major surface. The single crystal layer is provided directly on the major surface of the substrate to cover the protrusion, and includes a crack therein. The nitride semiconductor layer is provided on the single crystal layer.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: August 6, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideto Sugawara, Masaaki Onomura
  • Publication number: 20130065341
    Abstract: According to one embodiment, a method for fabricating a stacked nitride-compound semiconductor structure includes forming a first protection film on a second surface of a substrate, forming a first nitride-compound semiconductor layer on the first surface of the substrate, forming a second protection film on the first nitride-compound semiconductor layer, removing the first protection film to expose the second surface of the substrate, forming a second nitride-compound semiconductor layer on the second surface of the substrate, and removing the second protection film to expose the first surface of the second nitride-compound semiconductor layer.
    Type: Application
    Filed: March 9, 2012
    Publication date: March 14, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro KAI, Hideto Sugawara
  • Publication number: 20120211784
    Abstract: According to one embodiment, a nitride semiconductor stacked structure having a first surface includes a substrate, a first buffer layer, a first crystal layer, a second buffer layer and a second crystal layer. A step portion is provided in the substrate and includes an upper surface, a lower surface, and a side surface between the upper surface and the lower surface. The first buffer layer includes InsAltGa1-s-tN (0?s?0.05, 0?t?1) and covers the lower surface and the side surface. The first crystal layer is provided on the first buffer layer, includes InsAltGa1-s-tN (0?s?0.05, 0?t?0.05), and has an upper surface provided above the upper surface of the substrate. The second buffer layer includes InsAltGa1-s-tN (0?s?0.05, 0?t?1) and continuously covers the upper surface of the first crystal layer and the upper surface of the substrate. The second crystal layer covers the second buffer layer, includes InsAltGa1-s-tN (0?s?0.05, 0?t?0.05), and has the first surface.
    Type: Application
    Filed: September 1, 2011
    Publication date: August 23, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hideto Sugawara
  • Patent number: 8247794
    Abstract: According to one embodiment, a nitride semiconductor device includes a substrate, an Alx1Ga1-x1N first buried layer, an InyAlzGa1-y-zN buried layer and an Alx2Ga1-x2N second buried layer. The substrate has protrusions formed in an in-plane direction on a first major surface, and a depression between adjacent ones of the protrusions. The first buried layer is formed on the depression and one of the protrusions. The InyAlzGa1-y-zN buried layer is formed on the first buried layer. The second buried layer is formed on the InyAlzGa1-y-zN buried layer. A portion of the first buried layer formed on the depression and a portion of the first buried layer formed on the one of the protrusions are not connected to each other. A portion of the InyAlzGa1-y-zN buried layer formed above the depression and a portion of the InyAlzGa1-y-zN buried layer formed above the one of the protrusions are connected to each other.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: August 21, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideto Sugawara
  • Publication number: 20120153439
    Abstract: According to one embodiment, stacked layers of a nitride semiconductor include a substrate, a single crystal layer and a nitride semiconductor layer. The substrate does not include a nitride semiconductor and has a protrusion on a major surface. The single crystal layer is provided directly on the major surface of the substrate to cover the protrusion, and includes a crack therein. The nitride semiconductor layer is provided on the single crystal layer.
    Type: Application
    Filed: May 6, 2011
    Publication date: June 21, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideto Sugawara, Masaaki Onomura
  • Patent number: 8193021
    Abstract: A nitride semiconductor includes: a substrate having a major surface including a first crystal polarity surface and a second crystal polarity surface different from the first crystal polarity surface; and a single polarity layer provided above the major surface and having a single crystal polarity.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: June 5, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideto Sugawara
  • Publication number: 20110309329
    Abstract: According to one embodiment, a nitride semiconductor device includes a substrate, an Alx1Ga1-x1N first buried layer, an InyAlzGa1-y-zN buried layer and an Alx2Ga1-x2N second buried layer. The substrate has protrusions formed in an in-plane direction on a first major surface, and a depression between adjacent ones of the protrusions. The first buried layer is formed on the depression and one of the protrusions. The InyAlzGa1-y-zN buried layer is formed on the first buried layer. The second buried layer is formed on the InyAlzGa1-y-zN buried layer. A portion of the first buried layer formed on the depression and a portion of the first buried layer formed on the one of the protrusions are not connected to each other. A portion of the InyAlzGa1-y-zN buried layer formed above the depression and a portion of the InyAlzGa1-y-zN buried layer formed above the one of the protrusions are connected to each other.
    Type: Application
    Filed: November 23, 2010
    Publication date: December 22, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hideto Sugawara
  • Publication number: 20110250714
    Abstract: A nitride semiconductor includes: a substrate having a major surface including a first crystal polarity surface and a second crystal polarity surface different from the first crystal polarity surface; and a single polarity layer provided above the major surface and having a single crystal polarity.
    Type: Application
    Filed: June 23, 2011
    Publication date: October 13, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hideto Sugawara
  • Patent number: 8004065
    Abstract: A nitride semiconductor includes: a substrate having a major surface including a first crystal polarity surface and a second crystal polarity surface different from the first crystal polarity surface; and a single polarity layer provided above the major surface and having a single crystal polarity.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: August 23, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideto Sugawara
  • Patent number: 7714350
    Abstract: A gallium nitride based semiconductor device comprises: a first gallium nitride based semiconductor film doped with magnesium; and a second gallium nitride based semiconductor film provided on the first gallium nitride based semiconductor film and doped with magnesium. The first gallium nitride based semiconductor film has substantially flat distributions of magnesium concentration and hydrogen atom concentration, and the magnesium concentration is higher than the hydrogen atom concentration. The second gallium nitride based semiconductor film has a first region in which the magnesium concentration decreases and the hydrogen atom concentration increases toward the surface, and the magnesium concentration in the first region is higher than the hydrogen atom concentration in the first region and higher than the magnesium concentration in the first gallium nitride based semiconductor film.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: May 11, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideto Sugawara, Chie Hongo
  • Patent number: 7550368
    Abstract: A group-III nitride semiconductor stack comprises a single-crystal substrate, a first group-III nitride layer formed on a principal surface of the single-crystal substrate, a graded low-temperature deposited layer formed on the group-III nitride layer and made of nitride in which group-III element composition is continuously changed, and a second group-III nitride layer formed on the graded low-temperature deposited layer.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: June 23, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideto Sugawara, Tsunenori Hiratsuka
  • Publication number: 20090101935
    Abstract: A nitride semiconductor includes: a substrate having a major surface including a first crystal polarity surface and a second crystal polarity surface different from the first crystal polarity surface; and a single polarity layer provided above the major surface and having a single crystal polarity.
    Type: Application
    Filed: October 14, 2008
    Publication date: April 23, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hideto Sugawara
  • Publication number: 20080268558
    Abstract: A high-luminance light emitting element is manufactured by a method comprising: forming a light emitting layer on a first surface of a GaP substrate including the first surface and a second surface opposed to the first surface and having an area smaller than the first area, the light emitting layer emitting light of a wavelength ? permitted to pass through the GaP substrate; forming a plurality of side surfaces on the GaP substrate to be respectively aslant by substantially the same angle to become narrower toward the second surface; and forming a plurality of depressions and protrusions as high as 0.1? to 3? on the side surfaces.
    Type: Application
    Filed: October 19, 2007
    Publication date: October 30, 2008
    Inventors: Hideto Sugawara, Yukio Watanabe, Hirohisa Abe, Kuniaki Konno