Patents by Inventor Hidetoshi Fujimoto
Hidetoshi Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8581301Abstract: According to one embodiment, a nitride semiconductor device has an electroconductive substrate, a first nitride semiconductor layer provided directly on the electroconductive substrate or provided on the electroconductive substrate through a buffer layer and formed of a non-doped nitride semiconductor, a second nitride semiconductor layer provided on the first nitride semiconductor layer and formed of a non-doped or n-type nitride semiconductor having a band gap wider than that of the first nitride semiconductor layer, a heterojunction field effect transistor having a source electrode, a drain electrode, and a gate electrode, a Schottky barrier diode having an anode electrode and a cathode electrode, first and second element isolation insulating layers, and a frame electrode. The frame electrode is electrically connected to the source electrode and the electroconductive substrate, and surrounds outer peripheries of the heterojunction field effect transistor and the Schottky barrier diode.Type: GrantFiled: August 30, 2012Date of Patent: November 12, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Yasunobu Saito, Hidetoshi Fujimoto, Akira Yoshioka, Tetsuya Ohno, Toshiyuki Naka
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Patent number: 8577609Abstract: A map data is disclosed. The map data comprises a link data and a segment data. The link data describes a characteristic of each link in a group of links on a link-by-link basis. The group of links forms a road network. The segment data relates to each segment in a group of segments on a segment-by-segment basis. The segments are defined in units of link string. Each link string is a string of multiple links and corresponds to a main road. Each link string terminates at least at an intersection of the main road. The multiple links are a part of the group of links. The segment data of each segment describes information on a storage destination of the link data corresponding to the link string that forms the each segment.Type: GrantFiled: February 7, 2012Date of Patent: November 5, 2013Assignee: DENSO CORPORATIONInventor: Hidetoshi Fujimoto
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Patent number: 8560573Abstract: A map difference data generation apparatus includes: most recent and supplementary map data storage devices storing primary most recent and supplementary map data, respectively; a map update reflection device generating secondly most recent and supplementary map data according to an update of a first link, and generating tertiary most recent and supplementary map data according to an update of a second link; a determination device determining a dependency relationship between the update of the first and second links, in accordance with results of searching a route in the tertiary most recent and supplementary map data between first and second nodes, which are both ends of the second link; and a map difference data generation device generating map difference data, which defines a combination of the update of the first and second links, when the update of the first and second links have the dependency relationship.Type: GrantFiled: July 25, 2012Date of Patent: October 15, 2013Assignees: Denso Corporation, Kousokuya, Inc.Inventors: Takayuki Watanabe, Hidetoshi Fujimoto, Takamitsu Suzuki, Takayuki Suzuki, Kaoru Shibata, Akio Samizu
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Publication number: 20130248931Abstract: According to one embodiment, a nitride semiconductor device has an electroconductive substrate, a first nitride semiconductor layer provided directly on the electroconductive substrate or provided on the electroconductive substrate through a buffer layer and formed of a non-doped nitride semiconductor, a second nitride semiconductor layer provided on the first nitride semiconductor layer and formed of a non-doped or n-type nitride semiconductor having a band gap wider than that of the first nitride semiconductor layer, a heterojunction field effect transistor having a source electrode, a drain electrode, and a gate electrode, a Schottky barrier diode having an anode electrode and a cathode electrode, first and second element isolation insulating layers, and a frame electrode. The frame electrode is electrically connected to the source electrode and the electroconductive substrate, and surrounds outer peripheries of the heterojunction field effect transistor and the Schottky barrier diode.Type: ApplicationFiled: August 30, 2012Publication date: September 26, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Wataru SAITO, Yasunobu SAITO, Hidetoshi FUJIMOTO, Akira YOSHIOKA, Tetsuya OHNO, Toshiyuki NAKA
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Patent number: 8543618Abstract: In map data having link information, each of the links has reference information regarding a start point node of the link, a next link in a series of links, and an upper link. Further, links are memorized in a form of link list, and the position of the link in the link list is not changed in the course of adding/deleting a link, thereby enabling a direct reference to each of the links in the link list by the position of the link. The link information organized in the above-described manner enables the ease of the update of the map data as well as the speed-up of the calculation of, for example, a navigation route.Type: GrantFiled: July 9, 2009Date of Patent: September 24, 2013Assignees: DENSO CORPORATION, Kousokuya, Inc.Inventors: Hidetoshi Fujimoto, Toshio Nomura, Yasutaka Atarashi, Toshio Shinjo, Akio Samizu
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Publication number: 20130240899Abstract: According to one embodiment a nitride semiconductor device includes a first, a second and a third semiconductor layer, a first and a second main electrode and a control electrode. The first layer made of a nitride semiconductor of a first conductivity type is provided on a substrate. The second layer made of a nitride semiconductor of a second conductivity type is provided on the first layer. The third layer made of a nitride semiconductor is provided on the second layer. The first electrode is electrically connected with the second layer. The second electrode is provided at a distance from the first electrode and electrically connected with the second layer. The control electrode is provided within a first trench via an insulating film. The first trench is disposed between the first and the second main electrodes, penetrates the third and the second layers, and reaches the first layer.Type: ApplicationFiled: April 29, 2013Publication date: September 19, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Akira Yoshioka, Wataru Saito, Yasunobu Saito, Hidetoshi Fujimoto, Tetsuya Ohno
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Patent number: 8519439Abstract: According to one embodiment, the semiconductor element includes a first semiconductor layer. The first semiconductor layer contains AlXGa1-XN. A top layer of the first semiconductor layer is terminated by nitrogen. The semiconductor element includes a second semiconductor layer containing non-doped or first conductivity-type AlYGa1-YN formed on the first semiconductor layer. The semiconductor element includes a third semiconductor layer containing AlZGa1-ZN formed on the second semiconductor layer. The semiconductor element includes a first major electrode connected to the third semiconductor layer. The semiconductor element includes a second major electrode connected to the third semiconductor layer. The semiconductor element includes a gate electrode provided on the third semiconductor layer between the first major electrode and the second major electrode.Type: GrantFiled: September 21, 2011Date of Patent: August 27, 2013Assignee: Kabuhiki Kaisha ToshibaInventors: Wataru Saito, Hidetoshi Fujimoto
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Publication number: 20130069117Abstract: A nitride semiconductor device includes a substrate, a first Inx1Ga1-x1-y1Aly1N layer, a second Inx2Ga1-x2-y2Aly2N layer, an interlayer insulating film, a source electrode, a drain electrode, a first gate electrode, a Schottky electrode, a second gate electrode, an interconnection layer. The second Inx2Ga1-x2-y2Aly2N layer is provided on a surface of the first Inx1Ga1-x1-y1Aly1N layer. The second Inx2Ga1-x2-y2Aly2N layer has a wider band gap than the first Inx1Ga1-x1-y1Aly1N layer. The first gate electrode is provided between the source electrode and the drain electrode on a surface of the second Inx2Ga1-x2-y2Aly2N layer. The Schottky electrode is provided on the second Inx2Ga1-x2-y2Aly2N layer between the first gate electrode and the drain electrode. The second gate electrode is provided on the second Inx2Ga1-x2-y2Aly2N layer between the Schottky electrode and the drain electrode. The interconnection layer electrically connects the source electrode, the Schottky electrode, and the second gate electrode.Type: ApplicationFiled: September 14, 2012Publication date: March 21, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Akira YOSHIOKA, Yasunobu Saito, Hidetoshi Fujimoto, Tetsuya Ohno, Wataru Saito
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Publication number: 20130062671Abstract: A nitride semiconductor device includes a first semiconductor layer, a second semiconductor layer, a conductive substrate, a first electrode, a second electrode, and a control electrode. The second semiconductor layer is directly bonded to the first semiconductor layer. The conductive substrate is provided on and electrically connected to the first semiconductor layer. The first electrode and the second electrode are provided on and electrically connected to a surface of the second semiconductor layer on a side opposite to the first semiconductor layer. The control electrode is provided on the surface of the second semiconductor layer between the first electrode and the second electrode. The first electrode is electrically connected to a drain electrode of a MOSFET formed of Si. The control electrode is electrically connected to a source electrode of the MOSFET. The conductive substrate is electrically connected to a gate electrode of the MOSFET.Type: ApplicationFiled: March 14, 2012Publication date: March 14, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Wataru SAITO, Yasunobu Saito, Hidetoshi Fujimoto, Akira Yoshioka, Testsuya Ohno
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Patent number: 8390030Abstract: A semiconductor device includes: a first semiconductor layer made of an AlxGa1?xN (0?×<1); a second semiconductor layer provided on the first semiconductor layer and made of an undoped or first conductivity type AlyGa1?yN (0<y?1, x<y); an anode electrode and a cathode electrode which are connected to the second semiconductor layer; and a third semiconductor layer of second conductivity type provided between the anode electrode and the cathode electrode when viewed from a direction perpendicular to an upper surface of the second semiconductor layer. The third semiconductor layer is depleted when a predetermined magnitude or more of voltage is applied between the anode electrode and the cathode electrode.Type: GrantFiled: April 17, 2008Date of Patent: March 5, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Hidetoshi Fujimoto, Takao Noda, Yasunobu Saito, Tomohiro Nitta
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Publication number: 20130031049Abstract: A map difference data generation apparatus includes: most recent and supplementary map data storage devices storing primary most recent and supplementary map data, respectively; a map update reflection device generating secondly most recent and supplementary map data according to an update of a first link, and generating tertiary most recent and supplementary map data according to an update of a second link; a determination device determining a dependency relationship between the update of the first and second links, in accordance with results of searching a route in the tertiary most recent and supplementary map data between first and second nodes, which are both ends of the second link; and a map difference data generation device generating map difference data, which defines a combination of the update of the first and second links, when the update of the first and second links have the dependency relationship.Type: ApplicationFiled: July 25, 2012Publication date: January 31, 2013Applicants: Kousokuya, Inc., DENSO CORPORATIONInventors: Takayuki Watanabe, Hidetoshi Fujimoto, Takamitsu Suzuki, Takayuki Suzuki, Kaoru Shibata, Akio Samizu
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Publication number: 20120241751Abstract: According to one embodiment, a nitride semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first electrode, a second electrode, a third electrode, a first insulating film and a second insulating film. The first semiconductor layer includes a nitride semiconductor. The second semiconductor layer is provided on the first layer, includes a nitride semiconductor, and includes a hole. The first electrode is provided in the hole. The second electrode is provided on the second layer. The third electrode is provided on the second layer so that the first electrode is disposed between the third and second electrodes. The first insulating film is provided between the first electrode and an inner wall of the hole and between the first and second electrodes, and is provided spaced from the third electrode. The second insulating film is provided in contact with the second layer between the first and third electrodes.Type: ApplicationFiled: September 21, 2011Publication date: September 27, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Akira YOSHIOKA, Yasunobu Saito, Hidetoshi Fujimoto, Tetsuya Ohno, Wataru Saito, Toru Sugiyama
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Publication number: 20120203458Abstract: A map data is disclosed. The map data comprises a link data and a segment data. The link data describes a characteristic of each link in a group of links on a link-by-link basis. The group of links forms a road network. The segment data relates to each segment in a group of segments on a segment-by-segment basis. The segments are defined in units of link string. Each link string is a string of multiple links and corresponds to a main road. Each link string terminates at least at an intersection of the main road. The multiple links are a part of the group of links. The segment data of each segment describes information on a storage destination of the link data corresponding to the link string that forms the each segment.Type: ApplicationFiled: February 7, 2012Publication date: August 9, 2012Applicant: DENSO CORPORATIONInventor: Hidetoshi FUJIMOTO
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Publication number: 20120187413Abstract: According to one embodiment, a nitride semiconductor device includes a first semiconductor, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a first electrode, a second electrode and a third electrode. The first, second and fourth semiconductor layers include a nitride semiconductor. The second semiconductor layer is provided on the first semiconductor layer, has a band gap not less than that of the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer. The third semiconductor layer is GaN. The fourth semiconductor layer is provided on the third semiconductor layer to have an interspace on a part of the third semiconductor layer, has a band gap not less than that of the second semiconductor layer. The first electrode is provided on a portion of the third semiconductor layer. The fourth semiconductor layer is not provided on the portion.Type: ApplicationFiled: September 21, 2011Publication date: July 26, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Yasunobu SAITO, Hidetoshi FUJIMOTO, Tetsuya OHNO, Akira YOSHIOKA, Wataru SAITO
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Publication number: 20120187452Abstract: According to one embodiment, the semiconductor element includes a first semiconductor layer. The first semiconductor layer contains AlXGa1-XN. A top layer of the first semiconductor layer is terminated by nitrogen. The semiconductor element includes a second semiconductor layer containing non-doped or first conductivity-type AlYGa1-YN formed on the first semiconductor layer. The semiconductor element includes a third semiconductor layer containing AlZGa1-ZN formed on the second semiconductor layer. The semiconductor element includes a first major electrode connected to the third semiconductor layer. The semiconductor element includes a second major electrode connected to the third semiconductor layer. The semiconductor element includes a gate electrode provided on the third semiconductor layer between the first major electrode and the second major electrode.Type: ApplicationFiled: September 21, 2011Publication date: July 26, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Hidetoshi Fujimoto
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Patent number: 8227834Abstract: A semiconductor device includes: a first semiconductor layer including AlXGa1-XN (0?X?1); a second semiconductor layer provided on the first semiconductor layer, including AlYGa1-YN (0?Y?1, X<Y), and having a larger bandgap than the first semiconductor layer; a source electrode provided on the second semiconductor layer; a drain electrode provided on the second semiconductor layer; and a gate electrode provided on the second semiconductor layer between the source electrode and the drain electrode. A region of the second semiconductor layer below the gate electrode at a depth short of the first semiconductor layer is doped with atoms to be negatively charged in the second semiconductor layer.Type: GrantFiled: August 26, 2011Date of Patent: July 24, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yasunobu Saito, Wataru Saito, Yorito Kakiuchi, Tomohiro Nitta, Akira Yoshioka, Tetsuya Ohno, Hidetoshi Fujimoto, Takao Noda
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Patent number: 8203172Abstract: A nitride semiconductor device includes: a first layer made of a first nitride semiconductor; a second layer provided on the first layer and made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor; a first electrode electrically connected to the second layer; a second electrode provided on the second layer and juxtaposed to the first electrode in a first direction; and a floating electrode provided on the second layer, the floating electrode including: a portion sandwiched by the second electrode in a second direction orthogonal to the first direction; and a portion protruding from the second electrode toward the first electrode.Type: GrantFiled: April 9, 2010Date of Patent: June 19, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Yasunobu Saito, Takao Noda, Hidetoshi Fujimoto, Tetsuya Ohno
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Publication number: 20120122258Abstract: One embodiment provides a method for manufacturing a semiconductor light emitting device, including: forming a semiconductor light emitting device wafer, by: forming a plurality of semiconductor layers on a principal surface of a substrate; and forming a P-type semiconductor layer on the semiconductor layers as an uppermost layer; and forming a plurality of surface irregularities on the P-type semiconductor layer, by putting the semiconductor light emitting device wafer into a heat treating furnace; and performing a heat treatment on the semiconductor light emitting device wafer with (i) a mixed gas of hydrogen and ammonia or (ii) a mixed gas of nitrogen and ammonia.Type: ApplicationFiled: March 18, 2011Publication date: May 17, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Koichi Nitta, Hidetoshi Fujimoto
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Patent number: RE44215Abstract: The present invention is intended to provide a semiconductor optoelectric device with high luminescent efficiency and a method of manufacturing the same. The semiconductor optoelectric device 18 according to the present invention is constructed by depositing compound-semiconductor layers 13 and 14 on a monocrystalline substrate 11 of a hexagonal close-packed structure. The shape of the monocrystalline substrate 11 is a parallelogram. Individual sides of the parallelogram are parallel to a <11-20> orientation. As the monocrystalline substrate, sapphire, zinc oxide or silicon carbide may be used. As the compound-semiconductor layers, an n-type GaN layer 13 and p-type GaN layer 14 may be used.Type: GrantFiled: October 11, 2011Date of Patent: May 14, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Masahiro Yamamoto, Hidetoshi Fujimoto, Yoshihiro Kokubun, Masayuki Ishikawa, Shinji Saito, Yukie Nishikawa, John Rennie
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Patent number: D691573Type: GrantFiled: June 20, 2012Date of Patent: October 15, 2013Assignee: Sharp Kabushiki KaishaInventors: Katsuhiro Iida, Yasutaka Shimamoto, Tohru Ohtani, Hidetoshi Fujimoto, Yuhsuke Totsuka, Takeshi Kodera, Keiichi Takao, Keiichiroh Aou