Patents by Inventor Hidetoshi Fujimoto
Hidetoshi Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110309413Abstract: A semiconductor device includes: a first semiconductor layer including AlXGa1-XN (0?X?1); a second semiconductor layer provided on the first semiconductor layer, including AlYGa1-YN (0?Y?1, X<Y), and having a larger bandgap than the first semiconductor layer; a source electrode provided on the second semiconductor layer; a drain electrode provided on the second semiconductor layer; and a gate electrode provided on the second semiconductor layer between the source electrode and the drain electrode. A region of the second semiconductor layer below the gate electrode at a depth short of the first semiconductor layer is doped with atoms to be negatively charged in the second semiconductor layer.Type: ApplicationFiled: August 26, 2011Publication date: December 22, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Yasunobu SAITO, Wataru SAITO, Yorito KAKIUCHI, Tomohiro NITTA, Akira YOSHIOKA, Totsuya OHNO, Hidetoshi FUJIMOTO, Takao NODA
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Publication number: 20110272708Abstract: According to one embodiment, a nitride semiconductor device includes a first, a second and a third semiconductor layer, a first and a second main electrode and a control electrode. The first layer made of a nitride semiconductor of a first conductivity type is provided on a substrate. The second layer made of a nitride semiconductor of a second conductivity type is provided on the first layer. The third layer made of a nitride semiconductor is provided on the second layer. The first electrode is electrically connected with the second layer. The second electrode is provided at a distance from the first electrode and electrically connected with the second layer. The control electrode is provided within a first trench via an insulating film. The first trench is disposed between the first and the second main electrodes, penetrates the third and the second layers, and reaches the first layer.Type: ApplicationFiled: March 21, 2011Publication date: November 10, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Akira Yoshioka, Wataru Saito, Yasunobu Saito, Hidetoshi Fujimoto, Tetsuya Ohno
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Patent number: 8030660Abstract: A semiconductor device includes: a first semiconductor layer including AlXGa1-XN (0?X?1); a second semiconductor layer provided on the first semiconductor layer, including AlYGa1-YN (0?Y?1, X<Y), and having a larger bandgap than the first semiconductor layer; a source electrode provided on the second semiconductor layer; a drain electrode provided on the second semiconductor layer; and a gate electrode provided on the second semiconductor layer between the source electrode and the drain electrode. A region of the second semiconductor layer below the gate electrode at a depth short of the first semiconductor layer is doped with atoms to be negatively charged in the second semiconductor layer.Type: GrantFiled: February 13, 2009Date of Patent: October 4, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yasunobu Saito, Wataru Saito, Yorito Kakiuchi, Tomohiro Nitta, Akira Yoshioka, Tetsuya Ohno, Hidetoshi Fujimoto, Takao Noda
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Publication number: 20110204380Abstract: According to an embodiment, in a nitride-based FET, a protrusion portion is formed at an upper portion of an undoped GaN layer by second recess etching. On the protrusion portion, an undoped AlGaN layer is provided which is formed by first recess etching the upper portion of the undoped AlGaN layer. A multilayer portion is composed of the protrusion portion of the undoped GaN layer, the undoped AlGaN layer, and an insulating film. A trench portion is formed by recess etching the insulating film, the undoped AlGaN layer and a surface of the undoped GaN layer. A gate insulating film is formed on the multilayer portion and the trench portion. A gate electrode is formed on the gate insulating film so as to cover the trench portion. A film thickness of the insulting film is set larger than that of the gate insulating film.Type: ApplicationFiled: February 22, 2011Publication date: August 25, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Akira YOSHIOKA, Yasunobu Saito, Hidetoshi Fujimoto, Tetsuya Ohno, Takao Noda
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Publication number: 20110191388Abstract: Map data includes, for each of multiple links used for representing a road in a map, a link record and a speed limit record for a certain link. The link records and the speed limit records of the multiple links for representing a road are collected to form separate data lists of respective attribute types, that is, a link record data list and a speed limit record data list, instead of collecting records by a unit of each link. The map data structured as separate attribute data lists of respective attribute data types for links in the map data, for example, establishes inter-attribute data association between different attribute data types for the certain link based on the arrangement orders of the respective attribute data types in the data list indicative of the same arrangement order of the multiple links.Type: ApplicationFiled: January 26, 2011Publication date: August 4, 2011Applicant: DENSO CORPORATIONInventors: Takayuki MATSUNAGA, Hidetoshi Fujimoto
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Publication number: 20100314666Abstract: A nitride semiconductor device includes: a first layer made of a first nitride semiconductor; a second layer provided on the first layer and made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor; a first electrode electrically connected to the second layer; a second electrode provided on the second layer and juxtaposed to the first electrode in a first direction; and a floating electrode provided on the second layer, the floating electrode including: a portion sandwiched by the second electrode in a second direction orthogonal to the first direction; and a portion protruding from the second electrode toward the first electrode.Type: ApplicationFiled: April 9, 2010Publication date: December 16, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Wataru SAITO, Yasunobu SAITO, Takao NODA, Hidetoshi FUJIMOTO, Tetsuya OHNO
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Patent number: 7805242Abstract: A control circuit detects a current position of a subject vehicle on a map. Before executing a driving assistance application, the control circuit computes a map reliability degree by using a positioning accuracy coefficient, a time-based change coefficient, and an information accuracy coefficient. The positioning accuracy coefficient indicates a positioning accuracy of map data with respect to a target spot. The time-based change coefficient indicates a time-based change of the map data from the latest investigation for the target spot. The information accuracy coefficient indicates an accordance ratio of the map data relative to actual data with respect to multiple information items related to the target spot. The map data can be used for executing the driving assistance application when the product of (i) a required accuracy designated to the application and (ii) the computed map reliability degree is equal to or more than a predetermined value.Type: GrantFiled: February 1, 2007Date of Patent: September 28, 2010Assignee: DENSO CORPORATIONInventor: Hidetoshi Fujimoto
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Patent number: 7728354Abstract: A semiconductor device includes: a first semiconductor layer of p-type AlxGa1-xN (0?x?1); a second semiconductor layer of n-type AlyGa1-yN (0<y<1, x<y) formed on the first semiconductor layer; a control electrode formed on the second semiconductor layer; a first main electrode connected to the first semiconductor layer and the second semiconductor layer; and a second main electrode connected to the second semiconductor layer. An interface between the first semiconductor layer and the second semiconductor layer has a surface orientation of (1-101) or (11-20).Type: GrantFiled: November 14, 2007Date of Patent: June 1, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Akira Yoshioka, Hidetoshi Fujimoto, Takao Noda, Yasunobu Saito, Tomohiro Nitta, Yorito Kakiuchi
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Patent number: 7680593Abstract: An information center has an all-road updating data and a main-road updating data. The all-road updating data is a difference of all roads extracted from an all-road map data, and the main-road updating map data is a difference of specified roads extracted from the all-road map data. A map display system executes a reverse-updating to return the map data to a previous state not updated with the main-road updated map data, when its map data has already been updated with the main-road updated map data. The map display system then executes updating of the map data with the all-road updated map data.Type: GrantFiled: March 1, 2007Date of Patent: March 16, 2010Assignees: DENSO CORPORATION, Robert Bosch GmbHInventor: Hidetoshi Fujimoto
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Publication number: 20100023554Abstract: In map data having link information, each of the links has reference information regarding a start point node of the link, a next link in a series of links, and an upper link. Further, links are memorized in a form of link list, and the position of the link in the link list is not changed in the course of adding/deleting a link, thereby enabling a direct reference to each of the links in the link list by the position of the link. The link information organized in the above-described manner enables the ease of the update of the map data as well as the speed-up of the calculation of, for example, a navigation route.Type: ApplicationFiled: July 9, 2009Publication date: January 28, 2010Applicants: DENSO CORPORATION, KOUSOKUYA, Inc.Inventors: Hidetoshi Fujimoto, Toshio Nomura, Yasutaka Atarashi, Toshio Shinjo, Akio Samizu
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Publication number: 20090200576Abstract: A semiconductor device includes: a first semiconductor layer including AlXGa1-XN (0?X?1); a second semiconductor layer provided on the first semiconductor layer, including AlYGa1-YN (0?Y?1, X<Y), and having a larger bandgap than the first semiconductor layer; a source electrode provided on the second semiconductor layer; a drain electrode provided on the second semiconductor layer; and a gate electrode provided on the second semiconductor layer between the source electrode and the drain electrode. A region of the second semiconductor layer below the gate electrode at a depth short of the first semiconductor layer is doped with atoms to be negatively charged in the second semiconductor layer.Type: ApplicationFiled: February 13, 2009Publication date: August 13, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Yasunobu Saito, Wataru Saito, Yorito Kakiuchi, Tomohiro Nitta, Akira Yoshioka, Tetsuya Ohno, Hidetoshi Fujimoto, Takao Noda
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Patent number: 7538366Abstract: A nitride semiconductor device includes: a conductive substrate; a first semiconductor layer provided on the substrate; a second semiconductor layer provided on the first semiconductor layer; a third semiconductor layer on the second semiconductor layer; a first main electrode connected to the third semiconductor layer; a second main electrode connected to the third semiconductor layer; and a control electrode provided on the third semiconductor layer. The first semiconductor layer is made of AlXGa1?XN (0?X?1) of a first conductivity type. The second semiconductor layer is made of a first nitride semiconductor. The third semiconductor layer is made of a second nitride semiconductor which is undoped or of n-type and has a wider bandgap than the first nitride semiconductor.Type: GrantFiled: April 25, 2007Date of Patent: May 26, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Akira Yoshioka, Hidetoshi Fujimoto, Yasunobu Saito, Takao Noda, Tomohiro Nitta, Yorito Kakiuchi
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Publication number: 20080277692Abstract: A semiconductor device includes: a first semiconductor layer made of an AlxGa1?xN (0?x<1); a second semiconductor layer provided on the first semiconductor layer and made of an undoped or first conductivity type AlyGa1?yN (0<y?1, x<y); an anode electrode and a cathode electrode which are connected to the second semiconductor layer; and a third semiconductor layer of second conductivity type provided between the anode electrode and the cathode electrode when viewed from a direction perpendicular to an upper surface of the second semiconductor layer. The third semiconductor layer is depleted when a predetermined magnitude or more of voltage is applied between the anode electrode and the cathode electrode.Type: ApplicationFiled: April 17, 2008Publication date: November 13, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Wataru Saito, Hidetoshi Fujimoto, Takao Noda, Yasunobu Saito, Tomohiro Nitta
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Publication number: 20080116486Abstract: A semiconductor device includes: a first semiconductor layer of p-type AlxGa1-xN (0?x?1); a second semiconductor layer of n-type AlyGa1-yN (0<y<1, x<y) formed on the first semiconductor layer; a control electrode formed on the second semiconductor layer; a first main electrode connected to the first semiconductor layer and the second semiconductor layer; and a second main electrode connected to the second semiconductor layer. An interface between the first semiconductor layer and the second semiconductor layer has a surface orientation of (1-101) or (11-20).Type: ApplicationFiled: November 14, 2007Publication date: May 22, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Wataru SAITO, Akira Yoshioka, Hidetoshi Fujimoto, Takao Noda, Yasunobu Saito, Tomohiro Nitta, Yorito Kakiuchi
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Publication number: 20070299606Abstract: A control circuit detects a current position of a subject vehicle on a map. Before executing a driving assistance application, the control circuit computes a map reliability degree by using a positioning accuracy coefficient, a time-based change coefficient, and an information accuracy coefficient. The positioning accuracy coefficient indicates a positioning accuracy of map data with respect to a target spot. The time-based change coefficient indicates a time-based change of the map data from the latest investigation for the target spot. The information accuracy coefficient indicates an accordance ratio of the map data relative to actual data with respect to multiple information items related to the target spot. The map data can be used for executing the driving assistance application when the product of (i) a required accuracy designated to the application and (ii) the computed map reliability degree is equal to or more than a predetermined value.Type: ApplicationFiled: February 1, 2007Publication date: December 27, 2007Applicant: DENSO CORPORATIONInventor: Hidetoshi Fujimoto
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Publication number: 20070254431Abstract: A nitride semiconductor device includes: a conductive substrate; a first semiconductor layer provided on the substrate; a second semiconductor layer provided on the first semiconductor layer; a third semiconductor layer on the second semiconductor layer; a first main electrode connected to the third semiconductor layer; a second main electrode connected to the third semiconductor layer; and a control electrode provided on the third semiconductor layer. The first semiconductor layer is made of AlXGa1?XN (0?X?1) of a first conductivity type. The second semiconductor layer is made of a first nitride semiconductor. The third semiconductor layer is made of a second nitride semiconductor which is undoped or of n-type and has a wider bandgap than the first nitride semiconductor.Type: ApplicationFiled: April 25, 2007Publication date: November 1, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Wataru Saito, Akira Yoshioka, Hidetoshi Fujimoto, Yasunobu Saito, Takao Noda, Tomohiro Nitta, Yorito Kakiuchi
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Publication number: 20070208505Abstract: An information center has an all-road updating data and a main-road updating data. The all-road updating data is a difference of all roads extracted from an all-road map data, and the main-road updating map data is a difference of specified roads extracted from the all-road map data. A map display system executes a reverse-updating to return the map data to a previous state not updated with the main-road updated map data, when its map data has already been updated with the main-road updated map data. The map display system then executes updating of the map data with the all-road updated map data.Type: ApplicationFiled: March 1, 2007Publication date: September 6, 2007Applicants: DENSO CORPORATION, ROBERT BOSCH GmbHInventor: Hidetoshi Fujimoto
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Patent number: 7157749Abstract: A bipolar transistor is provided which includes a GaAs substrate, an n-type collector region formed on the GaAs substrate, a p-type base region formed on the n-type collector region and having a p-type base layer of SiGe having a composition lattice-matched with the GaAs substrate, and an n-type emitter region formed on the p-type base region. A bipolar transistor may include a GaAs substrate, a collector region of a first conductivity type formed on the GaAs substrate and including a collector contact layer of the first conductivity type SiGe, which has a composition lattice-matched with the GaAs substrate, a base region of a second conductivity type formed on the collector region of the first conductivity type, and an emitter region of the first conductivity type formed on the base region of the second conductivity type.Type: GrantFiled: February 9, 2005Date of Patent: January 2, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Hidetoshi Fujimoto, Tetsuro Nozu, Yoshitomo Sagae, Akira Yoshioka
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Publication number: 20050249348Abstract: Encryption is executed with respect to an encryption target unit based on an encryption ratio with maintaining the same data length both prior to and subsequent to the encryption process. In Pattern 1, one third from the encryption target unit is encrypted, while two thirds (the rest) of the encryption target unit are not encrypted. In Pattern 2, three sub-patterns P1, P2, P3 that have different encryption ratios are applied. The sub-patterns P1, P2, P3 have the encryption ratios of 50%, 25%, and 75%, respectively. In Pattern 3, three sub-patterns P11, P12, P13 that have different encryption starting points in addition to the different encryption ratios are applied. The sub-patterns P11, P12, P13 encrypt based on encryption ratios of 50%, 25%, and 75% from 25%, 50%, and 0% subsequent to the beginning of the unit.Type: ApplicationFiled: July 9, 2003Publication date: November 10, 2005Inventors: Hidetoshi Fujimoto, Masahiro Kimura
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Publication number: 20050189565Abstract: A bipolar transistor is provided which includes a GaAs substrate, an n-type collector region formed on the GaAs substrate, a p-type base region formed on the n-type collector region and having a p-type base layer of SiGe having a composition lattice-matched with the GaAs substrate, and an n-type emitter region formed on the p-type base region. A bipolar transistor may include a GaAs substrate, a collector region of a first conductivity type formed on the GaAs substrate and including a collector contact layer of the first conductivity type SiGe, which has a composition lattice-matched with the GaAs substrate, a base region of a second conductivity type formed on the collector region of the first conductivity type, and an emitter region of the first conductivity type formed on the base region of the second conductivity type.Type: ApplicationFiled: February 9, 2005Publication date: September 1, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hidetoshi Fujimoto, Tetsuro Nozu, Yoshitomo Sagae, Akira Yoshioka