Patents by Inventor Hidetoshi Tanaka
Hidetoshi Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967993Abstract: Provided is a communication apparatus for making connection to a communication network, including: an optical network unit; and an external power supply input/output terminal, the communication apparatus being configured such that electrical power is fed to the optical network unit from an external terminal that is connected to the external power supply input/output terminal and functions as an auxiliary power supply.Type: GrantFiled: October 31, 2019Date of Patent: April 23, 2024Assignee: Nippon Telegraph and Telephone CorporationInventors: Toshimitsu Tanaka, Naoki Hanaoka, Toshihiro Hayashi, Hiroya Minami, Hidetoshi Takada
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Publication number: 20240102089Abstract: The purpose of the present invention is to provide a method for conveniently and accurately evaluating the ligation efficiency in the DNA sequencing process in order to optimize the condition of ligating Y-type adapters to both ends of a double-stranded DNA fragment. The present invention relates to a method for evaluating the efficiency of ligation reaction through which Y-type adapters are ligated to both ends of DNA to be analyzed, in the sequencing process of DNA to be analyzed using the Y-type adapter, wherein the efficiency of reaction is evaluated by electrophoresing a reaction mixture containing ligation molecules, between the DNA and the Y-type adapters, produced by the ligation reaction under a specified condition, and analyzing a band separated on the basis of the number of adapters ligated to the DNA.Type: ApplicationFiled: December 15, 2021Publication date: March 28, 2024Inventors: Masafumi Tanaka, Hidetoshi Inoko
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Publication number: 20240072058Abstract: In a semiconductor integrated circuit device, an output circuit includes a first transistor connected between VSS and an output terminal. A first power line supplying VSS is formed in a buried interconnect layer, and above the buried interconnect layer, a second power line supplying VSS is formed in an M1 interconnect layer and a third power line connected to the second power line is formed in an M2 interconnect layer. A first output interconnect is formed in the M1 interconnect layer, and a second output interconnect connected to the first output interconnect is formed in the M2 interconnect layer.Type: ApplicationFiled: October 18, 2023Publication date: February 29, 2024Inventors: Isaya SOBUE, Hidetoshi TANAKA
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Patent number: 11905443Abstract: To provide a quantum dot-containing resin sheet or film, a method for producing the same, and a wavelength conversion member that can, in particular, solve the problem of aggregation of the quantum dots and the problem with the use of a scattering agent, suppress a decrease in light conversion efficiency, and improve the light conversion efficiency of a resin molded product containing quantum dots. The quantum dot-containing resin sheet or film of the present invention includes a stack of a plurality of resin layers, at least one of the resin layers containing quantum dots, and the plurality of resin layers is integrally molded through co-extrusion.Type: GrantFiled: March 1, 2023Date of Patent: February 20, 2024Assignee: NS MATERIALS INC.Inventors: Kazunori Iida, Emi Tsutsumi, Mika Niwaki, Jun Kaneno, Soichiro Nikata, Hidetoshi Tanaka
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Publication number: 20240038757Abstract: In a semiconductor integrated circuit device, first and second interconnects extending in the X direction are formed in a metal interconnect layer. The first and second interconnects are placed on the opposite sides of each resistor element in the X direction and connected to the resistor element. The first interconnect is connected to PAD, and a third interconnect is connected to VSS. In an ESD protection diode, an anode and a cathode are formed alternately in the Y direction. The resistor element and the first and second interconnects overlap the cathode of the ESD protection diode, and the third interconnect overlaps the anode of the ESD protection diode, in planar view.Type: ApplicationFiled: September 28, 2023Publication date: February 1, 2024Inventor: Hidetoshi TANAKA
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Patent number: 11824055Abstract: In an output circuit of a semiconductor integrated circuit device, an output transistor is placed apart from an ESD protection diode connected to an external output terminal, and a protection resistance is placed between them. The protection resistance is formed as a plurality of separate resistance regions, and taps supplying a power supply voltage to a substrate or a well are formed between the resistance regions. Noise applied to the external output terminal is attenuated by the protection resistance before reaching the output transistor and absorbed through the taps.Type: GrantFiled: May 2, 2022Date of Patent: November 21, 2023Assignee: SOCIONEXT INC.Inventor: Hidetoshi Tanaka
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Patent number: 11699660Abstract: A semiconductor integrated circuit device includes a core region and an IO region on a chip. In an IO cell row placed in the IO region, a first power supply line extending in the X direction in a low power supply voltage region has a portion protruding to the core region. A signal IO cell has a reinforcing line that connects a second power supply line extending in the X direction in the low power supply voltage region and a third power supply line extending in the X direction in a high power supply voltage region, the reinforcing line extending in the Y direction in a layer above the second and third power supply lines.Type: GrantFiled: February 19, 2021Date of Patent: July 11, 2023Assignee: SOCIONEXT INC.Inventors: Isaya Sobue, Hidetoshi Tanaka, Mai Tsukamoto
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Publication number: 20230203366Abstract: To provide a quantum dot-containing resin sheet or film, a method for producing the same, and a wavelength conversion member that can, in particular, solve the problem of aggregation of the quantum dots and the problem with the use of a scattering agent, suppress a decrease in light conversion efficiency, and improve the light conversion efficiency of a resin molded product containing quantum dots. The quantum dot-containing resin sheet or film of the present invention includes a stack of a plurality of resin layers, at least one of the resin layers containing quantum dots, and the plurality of resin layers is integrally molded through co-extrusion.Type: ApplicationFiled: March 1, 2023Publication date: June 29, 2023Applicant: NS MATERIALS INC.Inventors: Kazunori IIDA, Emi TSUTSUMI, Mika NIWAKI, Jun KANENO, Soichiro NIKATA, Hidetoshi TANAKA
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Patent number: 11629288Abstract: To provide a quantum dot-containing resin sheet or film, a method for producing the same, and a wavelength conversion member that can, in particular, solve the problem of aggregation of the quantum dots and the problem with the use of a scattering agent, suppress a decrease in light conversion efficiency, and improve the light conversion efficiency of a resin molded product containing quantum dots. The quantum dot-containing resin sheet or film of the present invention includes a stack of a plurality of resin layers, at least one of the resin layers containing quantum dots, and the plurality of resin layers is integrally molded through co-extrusion.Type: GrantFiled: October 15, 2018Date of Patent: April 18, 2023Assignee: NS MATERIALS INC.Inventors: Kazunori Iida, Emi Tsutsumi, Mika Niwaki, Jun Kaneno, Soichiro Nikata, Hidetoshi Tanaka
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Patent number: 11581302Abstract: An ESD protection diode in a semiconductor device includes: a semiconductor substrate; a diode group that has a plurality of grouped VNW diodes, each of the VNW diodes having a VNW having a lower end and an upper end, that are formed on the semiconductor substrate and have a semiconductor material; and a top plate that is formed above the diode group and is a conductive layer electrically connected to the upper ends of the VNWs of the respective VNW diodes, and there is fabricated the semiconductor device that is capable of, even when large current flows through the VNW diode, suppressing current concentration and preventing damage of the VNW diode.Type: GrantFiled: August 21, 2020Date of Patent: February 14, 2023Assignee: SOCIONEXT INC.Inventor: Hidetoshi Tanaka
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Publication number: 20230006100Abstract: A stacked body includes a long side and a short side in a top view. The long side extends in a first direction. The short side extends in a second direction orthogonal to the first direction. The short side is shorter than the long side. A light emission peak wavelength of a first active layer is different from a light emission peak wavelength of a second active layer. A first n-type layer includes a first n-side contact portion contacting a first electrode. A second n-type layer includes a second n-side contact portion contacting a second electrode. In a top view, a center of the first n-side contact portion is separated from a first line that passes through a center of the second n-side contact portion and is parallel to the first direction.Type: ApplicationFiled: June 27, 2022Publication date: January 5, 2023Applicant: NICHIA CORPORATIONInventors: Hidetoshi TANAKA, Hirofumi NISHIYAMA, Kentaro YAGI
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Patent number: 11444079Abstract: A semiconductor device includes: a semiconductor substrate; a VNW transistor being a functional element provided with a first projection formed on the semiconductor substrate, having a semiconductor material, and having a lower end and an upper end; a dummy functional element provided with a second projection formed on the semiconductor substrate, having a semiconductor material, having a lower end and an upper end, and arranged side by side with the first projection; and a first wiring formed above the first projection and above the second projection, electrically connected to the upper end of the first projection, and electrically isolated from the upper end of the second projection. Consequently, the semiconductor device capable of suppressing variation in characteristics of the VNW transistors is realized.Type: GrantFiled: August 25, 2020Date of Patent: September 13, 2022Assignee: SOCIONEXT INC.Inventor: Hidetoshi Tanaka
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Publication number: 20220262787Abstract: In an output circuit of a semiconductor integrated circuit device, an output transistor is placed apart from an ESD protection diode connected to an external output terminal, and a protection resistance is placed between them. The protection resistance is formed as a plurality of separate resistance regions, and taps supplying a power supply voltage to a substrate or a well are formed between the resistance regions. Noise applied to the external output terminal is attenuated by the protection resistance before reaching the output transistor and absorbed through the taps.Type: ApplicationFiled: May 2, 2022Publication date: August 18, 2022Inventor: Hidetoshi TANAKA
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Publication number: 20220102586Abstract: A light-emitting element includes: a semiconductor stack having a triangular shape in a top plan view, the semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer between the first and seconds semiconductor layers; a first electrode located on the first semiconductor layer and including a first connecting portion and a first extension extending from the first connecting portion; and a second electrode located on the second semiconductor layer and including a second connecting portion and a second extension extending from the second connecting portion. The first extension includes a first portion extending from the first connecting portion toward the second connecting portion. The second extension includes a second portion including a portion extending along a first side, a third portion including a portion extending along a second side, and fourth and fifth portions each including a portion extending along a third side.Type: ApplicationFiled: September 20, 2021Publication date: March 31, 2022Applicant: NICHIA CORPORATIONInventors: Hiroshi FUJIMOTO, Keiji EMURA, Hidetoshi TANAKA
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Publication number: 20220077137Abstract: A semiconductor device includes a pad portion, a protection circuit, N wiring layers, and conductive vias connecting adjacent wiring layers, wherein, in a plan view, the semiconductor device includes a first area, a second area, and a third area, wherein the N wiring layers are provided to extend over the first area, the second area, and the third area, wherein a first wiring layer on a side of the pad portion is connected to the pad portion in the first area, and wherein an N-th wiring layer on a side of the protection circuit is connected to the protection circuit in the second area, and in the second area and the third area, where a total cross-sectional area of i-th conductive vias connecting an i-th wiring layer and an (i+1)-th wiring layer is denoted as Si, S1 is smaller than Sj for any j (j being 2 or more).Type: ApplicationFiled: September 3, 2021Publication date: March 10, 2022Inventors: Hidetoshi TANAKA, Mai Tsukamoto
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Patent number: 11063035Abstract: An ESD protection circuit includes a first fin structure having fins of a first conductivity type and a second fin structure having fins of a second conductivity type, the second fin structure being opposed to the first fin structure. A first power interconnect connected with the first fin structure and a signal interconnect connected with the second fin structure are formed in a first interconnect layer, and a second power interconnect connected with the first power interconnect is formed in a second interconnect layer. The width occupied by the second fin structure is greater than that of the first fin structure, and the width of the signal interconnect is greater than that of the first power interconnect.Type: GrantFiled: February 27, 2020Date of Patent: July 13, 2021Assignee: SOCIONEXT INC.Inventors: Chika Ito, Isaya Sobue, Hidetoshi Tanaka
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Publication number: 20210189230Abstract: To provide a quantum dot-containing resin sheet or film, a method for producing the same, and a wavelength conversion member that can, in particular, solve the problem of aggregation of the quantum dots and the problem with the use of a scattering agent, suppress a decrease in light conversion efficiency, and improve the light conversion efficiency of a resin molded product containing quantum dots. The quantum dot-containing resin sheet or film of the present invention includes a stack of a plurality of resin layers, at least one of the resin layers containing quantum dots, and the plurality of resin layers is integrally molded through co-extrusion.Type: ApplicationFiled: October 15, 2018Publication date: June 24, 2021Applicant: NS MATERIALS Inc.Inventors: Kazunori IIDA, Emi TSUTSUMI, Mika NIWAKI, Jun KANENO, Soichiro NIKATA, Hidetoshi TANAKA
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Publication number: 20210184035Abstract: A semiconductor device includes a semiconductor substrate and a resistance element provided above the semiconductor substrate, the resistance element includes a conductive pattern using a gate electrode film formed simultaneously with a gate electrode film arranged on a side surface of a semiconductor nanowire of a VNW transistor, and there is fabricated the semiconductor device that includes the VNW transistor having the semiconductor nanowire and the resistance element having sufficient electrical resistance.Type: ApplicationFiled: February 26, 2021Publication date: June 17, 2021Inventors: Hidetoshi TANAKA, Isaya SOBUE
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Publication number: 20210175172Abstract: A semiconductor integrated circuit device includes a core region and an IO region on a chip. In an IO cell row placed in the IO region, a first power supply line extending in the X direction in a low power supply voltage region has a portion protruding to the core region. A signal IO cell has a reinforcing line that connects a second power supply line extending in the X direction in the low power supply voltage region and a third power supply line extending in the X direction in a high power supply voltage region, the reinforcing line extending in the Y direction in a layer above the second and third power supply lines.Type: ApplicationFiled: February 19, 2021Publication date: June 10, 2021Inventors: Isaya SOBUE, Hidetoshi TANAKA, Mai TSUKAMOTO
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Publication number: 20210135045Abstract: A method of manufacturing a light-emitting device includes providing a structure body including a silicon substrate having a first portion, a second portion, and a third portion between the first portion and the second portion, and a first semiconductor layered body including a first light-emitting layer, the first semiconductor layered body being disposed on or above the silicon substrate. The method includes forming a first resin layer covering a lateral side of the silicon substrate and a lateral side of the first semiconductor layered body. The method includes a removal step of removing the first portion to expose a first surface of the first semiconductor layered body, removing the second portion to expose a second surface of the first semiconductor layered body, and leaving the third portion. The method includes forming a first wavelength conversion member on or above the first surface exposed by the removal of the first portion.Type: ApplicationFiled: October 23, 2020Publication date: May 6, 2021Applicant: NICHIA CORPORATIONInventor: Hidetoshi TANAKA