Patents by Inventor Hideyuki Arai

Hideyuki Arai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8558321
    Abstract: A semiconductor device includes: a first MIS transistor of a first conductivity type having a first active region as a region of a semiconductor substrate surrounded by an element isolation region formed in an upper portion of the semiconductor substrate, a first gate insulating film having a first high dielectric film formed on the first active region, and a first gate electrode formed on the first gate insulating film; and a resistance element having a second high dielectric film formed on the element isolation region and a resistance layer made of silicon formed on the second high dielectric film. The first high dielectric film and the second high dielectric film include the same high dielectric material, and the first high dielectric film includes a first adjustment metal, but the second high dielectric film does not include the first adjustment metal.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: October 15, 2013
    Assignee: Panasonic Corporation
    Inventors: Hiroji Shimizu, Yoshihiro Sato, Hideyuki Arai, Takayuki Yamada, Tsutomu Oosuka
  • Patent number: 8392856
    Abstract: A semiconductor device includes: a plurality of line features including at least one real feature which includes a gate electrode portion, and at least one dummy feature. Two of multiple ones of the dummy feature, and at least one of the line features interposed between the two dummy features and including the at least one real feature form parallel running line features which are evenly spaced. The parallel running line features have an identical width, and line end portions of the parallel running line features are substantially flush. Line end portion uniformization dummy features are formed on extensions of the line end portions of the parallel running line features. The line end portion uniformization dummy features include a plurality of linear features each having a same width as each of the line features and spaced at intervals equal to an interval between each adjacent pair of the line features.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: March 5, 2013
    Assignee: Panasonic Corporation
    Inventors: Akio Misaka, Yasuko Tabata, Hideyuki Arai, Takayuki Yamada
  • Patent number: 8374761
    Abstract: A driving force distribution control device for a four wheel drive vehicle having a mechanism that distributes the torque of an engine, which is transmitted to a main drive wheel, to a secondary drive wheel determines a first torque to be distributed to the secondary drive wheel on the basis of the engine torque, and corrects the determined first torque on the basis of a yaw rate deviation between a target yaw rate and an actual yaw rate of the vehicle. When an absolute value of the yaw rate deviation is equal to or greater than a predetermined value, the mechanism is controlled on the basis of the corrected torque.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: February 12, 2013
    Assignees: Nissan Motor Co., Ltd., Hitachi, Ltd.
    Inventors: Yoshiyuki Fukuda, Tomoaki Fujibayashi, Hideyuki Arai
  • Patent number: 8330248
    Abstract: A semiconductor device includes a circuit portion including at least one real feature, and a plurality of dummy feature groups each including a plurality of dummy features spaced apart from each other by a first distance. The plurality of dummy feature groups are spaced apart from each other by a second distance larger than the first distance, and the circuit portion and the plurality of dummy feature groups are spaced apart from each other by the second distance.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: December 11, 2012
    Assignee: Panasonic Corporation
    Inventors: Yasuko Tabata, Akio Misaka, Takehiro Hirai, Hideyuki Arai, Yuji Nonami
  • Publication number: 20110278679
    Abstract: A semiconductor device includes a circuit portion including at least one real feature, and a plurality of dummy feature groups each including a plurality of dummy features spaced apart from each other by a first distance. The plurality of dummy feature groups are spaced apart from each other by a second distance larger than the first distance, and the circuit portion and the plurality of dummy feature groups are spaced apart from each other by the second distance.
    Type: Application
    Filed: January 26, 2011
    Publication date: November 17, 2011
    Inventors: Yasuko Tabata, Akio Misaka, Takehiro Hirai, Hideyuki Arai, Yuji Nonami
  • Publication number: 20110272815
    Abstract: A semiconductor device includes: a plurality of line features including at least one real feature which includes a gate electrode portion, and at least one dummy feature. Two of multiple ones of the dummy feature, and at least one of the line features interposed between the two dummy features and including the at least one real feature form parallel running line features which are evenly spaced. The parallel running line features have an identical width, and line end portions of the parallel running line features are substantially flush. Line end portion uniformization dummy features are formed on extensions of the line end portions of the parallel running line features. The line end portion uniformization dummy features include a plurality of linear features each having a same width as each of the line features and spaced at intervals equal to an interval between each adjacent pair of the line features.
    Type: Application
    Filed: January 25, 2011
    Publication date: November 10, 2011
    Inventors: Akio Misaka, Yasuko Tabata, Hideyuki Arai, Takayuki Yamada
  • Publication number: 20110169100
    Abstract: A semiconductor device includes: a first MIS transistor of a first conductivity type having a first active region as a region of a semiconductor substrate surrounded by an element isolation region formed in an upper portion of the semiconductor substrate, a first gate insulating film having a first high dielectric film formed on the first active region, and a first gate electrode formed on the first gate insulating film; and a resistance element having a second high dielectric film formed on the element isolation region and a resistance layer made of silicon formed on the second high dielectric film. The first high dielectric film and the second high dielectric film include the same high dielectric material, and the first high dielectric film includes a first adjustment metal, but the second high dielectric film does not include the first adjustment metal.
    Type: Application
    Filed: January 12, 2011
    Publication date: July 14, 2011
    Inventors: Hiroji SHIMIZU, Yoshihiro Sato, Hideyuki Arai, Takayuki Yamada, Tsutomu Oosuka
  • Patent number: 7973835
    Abstract: This invention is to provide a solid-state image pickup apparatus including a photoelectric conversion unit (PD), transfer switch (MTX) for transferring signal charges from the photoelectric conversion unit, capacitance for holding the transferred signal charges, and amplification transistor (MSF) for outputting a signal corresponding to the signal charges held by the capacitance. The amplification transistor includes a capacitance unit (CFD) having the first capacitance value and an additive capacitance unit (Cox) for adding a capacitance to the capacitance unit to increase the first capacitance value and obtain the second capacitance value. A signal read-out from the amplification transistor has a first read-out mode in which a signal is read out while keeping the signal charges held by the capacitance unit and additive capacitance unit, and a second read-out mode in which a signal is read out while keeping the signal charges held by the capacitance unit.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: July 5, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventors: Katsuhito Sakurai, Shigetoshi Sugawa, Hideyuki Arai, Isamu Ueno, Katsuhisa Ogawa, Toru Koizumi, Tetsunobu Kochi, Hiroki Hiyama
  • Patent number: 7932153
    Abstract: A threshold control layer of a second MIS transistor is formed under the same conditions for forming a threshold control layer of a first MIS transistor. LLD regions of the second MIS transistor are formed under the same conditions for forming LDD regions of a third transistor.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: April 26, 2011
    Assignee: Panasonic Corporation
    Inventors: Takashi Nakabayashi, Hideyuki Arai, Mitsuo Nissa
  • Patent number: 7795662
    Abstract: A semiconductor memory device has a first interlayer insulating film formed on a semiconductor substrate and having a capacitor opening portion provided in the film, and a capacitance element formed over the bottom and sides of the capacitor opening portion and composed of a lower electrode, a capacitance insulating film, and an upper electrode. A bit-line contact plug is formed through the first interlayer insulating film. At least parts of respective upper edges of the lower electrode, the capacitance insulating film, and the upper electrode at a side facing the bit-line contact plug are located below the surface of the first interlayer insulating film, the lower electrode, the capacitance insulating film, and the upper electrode being located over the sides of the capacitor opening portion. The upper electrode is formed over only the bottom and sides of the capacitor opening portion.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: September 14, 2010
    Assignee: Panasonic Corporation
    Inventors: Hideyuki Arai, Takashi Nakabayashi
  • Patent number: 7763922
    Abstract: A capacitor of a semiconductor memory of the present invention includes: a lower electrode which covers the surface of a storage node hole from the bottom to at least one of the sidewalls up to a level lower than the top surface of a second interlayer insulating film; a capacitive insulating film which covers the lower electrode; and an upper electrode which covers the capacitive insulating film.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: July 27, 2010
    Assignee: Panasonic Corporation
    Inventors: Hideyuki Arai, Takashi Nakabayashi, Takashi Ohtsuka
  • Patent number: 7737480
    Abstract: A semiconductor memory device includes: a transistor formed in a substrate; a capacitor formed above one of source/drain regions of the transistor; a bit line formed above the substrate and extending in the gate length direction of the transistor; a first conductive plug connecting one of the source/drain regions and the capacitor; a second conductive plug connected to the other source/drain region that is not connected to the first conductive plug; and a third conductive plug formed on the second conductive plug and connected to the bit line. The central axis of the third conductive plug is displaced from the central axis of the second conductive plug in the gate width direction of the transistor.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: June 15, 2010
    Assignee: Panasonic Corporation
    Inventors: Ryo Nakagawa, Takashi Nakabayashi, Hideyuki Arai
  • Publication number: 20100047983
    Abstract: A threshold control layer of a second MIS transistor is formed under the same conditions for forming a threshold control layer of a first MIS transistor. LLD regions of the second MIS transistor are formed under the same conditions for forming LDD regions of a third transistor.
    Type: Application
    Filed: October 26, 2009
    Publication date: February 25, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Takashi NAKABAYASHI, Hideyuki Arai, Mitsuo Nissa
  • Patent number: 7622777
    Abstract: A threshold control layer of a second MIS transistor is formed under the same conditions for forming a threshold control layer of a first MIS transistor. LLD regions of the second MIS transistor are formed under the same conditions for forming LDD regions of a third transistor.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: November 24, 2009
    Assignee: Panasonic Corporation
    Inventors: Takashi Nakabayashi, Hideyuki Arai, Mitsuo Nissa
  • Patent number: 7517760
    Abstract: After protective insulating films are formed on first to third active regions, the protective insulating films formed on the first and third active regions are removed. Subsequently, an insulating film to be a first gate insulating film is formed on each of the first and third active regions, and then, the protective insulating film formed on the second active region is removed. Next, an insulating film to be a second gate insulating film is formed on the second active region, and then, the insulating film to be the first gate insulating film formed on the third active region is removed. Finally, an insulating film to be a third gate insulating film is formed on the third active region.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: April 14, 2009
    Assignee: Panasonic Corporation
    Inventors: Hideyuki Arai, Takashi Nakabayashi, Yasutoshi Okuno
  • Publication number: 20090043469
    Abstract: A driving force distribution control device for a four wheel drive vehicle having a mechanism that distributes the torque of an engine, which is transmitted to a main drive wheel, to a secondary drive wheel determines a first torque to be distributed to the secondary drive wheel on the basis of the engine torque, and corrects the determined first torque on the basis of a yaw rate deviation between a target yaw rate and an actual yaw rate of the vehicle. When an absolute value of the yaw rate deviation is equal to or greater than a predetermined value, the mechanism is controlled on the basis of the corrected torque.
    Type: Application
    Filed: August 5, 2008
    Publication date: February 12, 2009
    Inventors: Yoshiyuki FUKUDA, Hideyuki Arai, Tomoaki Fujibayashi
  • Patent number: 7386174
    Abstract: An image capture apparatus includes an image capture unit, a mode setting unit, a control unit, a wireless transmitting unit and a display unit. The image capture unit captures images. The mode setting unit is adapted to set one of a plurality of image capture modes in accordance with a selection by a user before the image capture unit captures the images. The control unit determines, according to the image capture mode set by the mode setting unit, three parameters to be applied to the captured images, the three parameters including a frame rate, the number of pixels, and a compression ratio. The wireless transmitting unit transmits the captured images by wireless after the three parameters determined by the control unit are applied to the captured images. The display unit displays the three parameters determined by the control unit.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: June 10, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuhiro Takahashi, Hideyuki Arai, Masamine Maeda
  • Publication number: 20080048234
    Abstract: A semiconductor memory device has a first interlayer insulating film formed on a semiconductor substrate and having a capacitor opening portion provided in the film, and a capacitance element formed over the bottom and sides of the capacitor opening portion and composed of a lower electrode, a capacitance insulating film, and an upper electrode. A bit-line contact plug is formed through the first interlayer insulating film. At least parts of respective upper edges of the lower electrode, the capacitance insulating film, and he upper electrode at a side facing the bit-line contact plug are located below the surface of the first interlayer insulating film, the lower electrode, the capacitance insulating film, and the upper electrode being located over the sides of the capacitor opening portion. The upper electrode is formed over only the bottom and sides of the capacitor opening portion.
    Type: Application
    Filed: July 11, 2007
    Publication date: February 28, 2008
    Inventors: Hideyuki Arai, Takashi Nakabayashi
  • Publication number: 20080035975
    Abstract: A semiconductor memory device includes: a transistor formed in a substrate; a capacitor formed above one of source/drain regions of the transistor; a bit line formed above the substrate and extending in the gate length direction of the transistor; a first conductive plug connecting one of the source/drain regions and the capacitor; a second conductive plug connected to the other source/drain region that is not connected to the first conductive plug; and a third conductive plug formed on the second conductive plug and connected to the bit line. The central axis of the third conductive plug is displaced from the central axis of the second conductive plug in the gate width direction of the transistor.
    Type: Application
    Filed: July 12, 2007
    Publication date: February 14, 2008
    Inventors: Ryo Nakagawa, Takashi Nakabayashi, Hideyuki Arai
  • Patent number: 7317475
    Abstract: This invention has as its object to appropriately inform the user of reception of an incoming call in accordance with the operation mode of a video camera upon arrival of call. To achieve this object, an apparatus has a telephone and video camera in a single housing, and comprises a device for muting a ringing tone during image sensing by the video camera.
    Type: Grant
    Filed: June 7, 2004
    Date of Patent: January 8, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideyuki Arai, Kazuhiro Takahashi