Abstract: A Unified Memory may store multiple types of content such as data or fast code or slow code. The data or code may be stored in separate arrays or in a common array. In an array, a tag bit may indicate the type of content such as data or fast code or slow code or single level or multilevel content. Tag bit may indicate communication interface or IO driver type. Sense amplifiers may be configurable based on the type of data being read. A Flash Security Measure is used to protect a protected memory area. A Flash Security Key is used for authentication and authorization a particular memory area. A XCAM (e.g., CAM) array is included in the Unified Memory. Unified Memory Concurrency is included.

Abstract: A ferrule assembly having highly protruding optical fibers and a corresponding method of efficiently, precisely and repeatedly fabricating the ferrule assemblies are provided. In this regard, a ferrule assembly is provided that includes a plurality of optical fibers extending at least about 3.5 ?m beyond the front face. The end portions of the optical fibers of the ferrule assembly may also be substantially coplanar with the end portions of the optical fibers differing in position from one another by no more than 100 nm. The ferrule assembly may be efficiently fabricated by polishing the optical fibers to a desired protrusion without first grinding or polishing the optical fibers to be flush with the front face of the ferrule. The ferrule assembly may be even more efficiently fabricated in instances in which the ferrule includes at least one polishing feature, such as an outwardly extending pedestal or a recessed portion.

Abstract: An integrated MIS capacitor has two substantially identical MIS capacitors. A first capacitor comprises a first region of a first conductivity type adjacent to a channel region of the first conductivity type in a semiconductor substrate. The semiconductor substrate has a second conductivity type. A gate electrode is insulated and spaced apart from the channel region of the first capacitor. The second capacitor is substantially identical to the first capacitor and is formed in the same semiconductor substrate. The gate electrode of the first capacitor is electrically connected to the first region of the second capacitor and the gate electrode of the second capacitor is electrically connected to the first region of the first capacitor. In this manner, the capacitors are connected in an anti-parallel configuration.

Abstract: A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal, a channel therebetween and a floating gate over at least a portion of the channel to control the conduction of electrons in the channel, and a control gate. The floating gate storage transistor can be in one of two states: a first state, such as erase, in which current can flow between the first terminal and the second terminal, and a second state, such as programmed, in which substantially no current flows between the first terminal and the second terminal. A pair of differential compare data lines connects to the control gate of each of the pair of non-volatile floating gate transistors.

Abstract: A plurality of packets associated with a plurality of protocols are received, wherein the plurality of packets are to be processed by a plurality of processors. Packets associated with a first protocol are sent to be processed by at least one of the plurality of processors before sending packets associated with a second protocol to be processed, in response to determining that the packets associated with the first protocol have a higher priority for processing than the packets associated with the first protocol.

Abstract: A fiber optic cable has a plug assembly that may be positioned and secured at any desired location along the length of the cable to engage a receptacle disposed within a connector port provided in a wall of a connection terminal. The plug assembly includes a shroud, a coupling nut, a heat shrink tube for sealing the cable and a boot for providing bending strain relief. At least a portion of the cable passes through the connector port for interconnection with optical fibers of a distribution cable or optical equipment. A method for routing a fiber optic cable into a connection terminal includes using a connector port provided in a wall of the terminal, determining a desired length of the cable, positioning and securing a plug assembly at a desired location along the length of the cable, and mating the plug assembly with a receptacle disposed within the connector port.

Abstract: A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.

Abstract: An isolation-less, contact-less nonvolatile memory array has a plurality of memory cells each with a floating gate for the storage of charges thereon, arranged in a plurality of rows and columns. Each memory cell can be of a number of different types. All the bit lines and source lines of the various embodiments are buried and are contact-less. In a first embodiment, each cell can be represented by a stacked gate floating gate transistor coupled to a separate assist transistor. The entire array can be planar; or in a preferred embodiment each of the floating gate transistors is in a trench; or each of the assist transistors is in a trench. In a second embodiment, each cell can be represented by a stacked gate floating gate transistor with the transistor in a trench. In a third embodiment, each cell can be represented by two stacked gate floating gate transistors coupled to a separate assist transistor, positioned between the two stacked gate floating gate transistors.

Abstract: The memory system includes a bitline leakage current compensation circuit for compensating for leakage current in an operational memory array by measuring the leakage current in a non-operational memory array or a dummy memory array and providing a feedback signal to a current source or providing the compensation current.

Abstract: A method and apparatus for debugging of OS kernel and applications software that does not require use of a hardware probe; can debug both user-mode programs and a significant body of the OS kernel code; allows the OS to continue servicing exceptions while debugging; leverages OS built-in device drivers for communicating devices to communicate with the host debugger; and can debug a production version of the OS kernel. When debugging is required, the running OS kernel dynamically loads a software-based debug agent on demand whereby such debug agent dynamically modifies the running production OS kernel code and data to intercept debugging traps and provide run-control. To provide debugging of loadable module, the debug agent implement techniques to intercept the OS module loading system call; set breakpoints in the loaded module initialization function; calculate the start address of the debugged module in memory; and asynchronously put the system under debug.

Abstract: A nonvolatile memory cell having a floating gate for the storage of charges thereon has a control gate and a separate erase gate. The cell is programmed by hot channel electron injection and is erased by poly to poly Fowler-Nordheim tunneling. A method for making an array of unidirectional cells in a planar substrate, as well as an array of bidirectional cells in a substrate having a trench, is disclosed. An array of such cells and a method of making such an array is also disclosed.

Abstract: A Unified Memory may store multiple types of content such as data or fast code or slow code. The data or code may be stored in separate arrays or in a common array. In an array, a tag bit may indicate the type of content such as data or fast code or slow code or single level or multilevel content. Tag bit may indicate communication interface or IO driver type. Sense amplifiers may be configurable based on the type of data being read. A Flash Security Measure is used to protect a protected memory area. A Flash Security Key is used for authentication and authorization a particular memory area. A XCAM (e.g., CAM) array is included in the Unified Memory. Unified Memory Concurrency is included.

Abstract: A multi-operational amplifier system comprises a plurality of operational amplifiers and a controller to configure the plurality of operational amplifiers. The operational amplifiers may be selectively configured to operate individually or in combination with other of the operational amplifiers. The operational amplifiers may have different common node inputs. In one aspect, the different inputs may be selected from groups of PMOS, N-type NMOS and NZ NMOS inputs. The operational amplifiers may include the different inputs that are arranged as differential pairs.

Abstract: A bandgap reference generator comprises a PMOS transistor and NMOS transistor in a pnp bipolar junction transistor connected in series in a first leg. The bandgap reference generator includes a second leg that includes a PMOS transistor, an NMOS transistor, a resistor and a pnp bipolar junction transistor. A bias circuit provides a bias to a mirror formed by the gates of the PMOS transistors to lower the operating voltage of the bandgap reference generator. A second biasing circuit may provide bias to the mirror formed of the NMOS transistors. A time-based and a DC bias-based start up circuitry and method is provided.

Abstract: A stacked gate nonvolatile memory floating gate device has a control gate. Programming of the cell in the array is accomplished by hot channel electron injection from the drain to the floating gate. Erasure occurs by Fowler-Nordheim tunneling of electrons from the floating gate to the control gate. Finally, to increase the density, each cell can be made in a trench.

Abstract: A high voltage generator provides high voltage signals with different regulated voltage levels. A charge pump generates the high voltage, and includes a quadrature phase forward and backward Vt-canceling high-voltage self-biasing charge pump with a powerup-assist diode. A high voltage series regulator generates the high voltage supply levels, and includes slew rate enhancement and trimmable diode regulation. A nested loop regulator eliminates shunt regulation.

Abstract: A high voltage generator provides high voltage signals with different regulated voltage levels. A charge pump generates the high voltage, and includes a quadrature phase forward and backward Vt-canceling high-voltage self-biasing charge pump with a powerup-assist diode. A high voltage series regulator generates the high voltage supply levels, and includes slew rate enhancement and trimmable diode regulation. A nested loop regulator eliminates shunt regulation.

Abstract: A preconnectorized outdoor cable streamlines the deployment of optical waveguides into the last mile of an optical network. The preconnectorized outdoor cable includes a cable and at least one plug connector. The plug connector is attached to a first end of the cable, thereby connectorizing at least one optical waveguide. The cable has at least one optical waveguide, at least one tensile element, and a cable jacket. Various cable designs such as figure-eight or flat cables may be used with the plug connector. In preferred embodiments, the plug connector includes a crimp assembly having a crimp housing and a crimp band. The crimp housing has two half-shells being held together by the crimp band for securing the at least one tensile element. When fully assembled, the crimp housing fits into a shroud of the preconnectorized cable. The shroud aides in mating the preconnectorized cable with a complimentary receptacle.

Abstract: A Unified Memory may store multiple types of content such as data or fast code or slow code. The data or code may be stored in separate arrays or in a common array. In an array, a tag bit may indicate the type of content such as data or fast code or slow code or single level or multilevel content. Tag bit may indicate communication interface or IO driver type. Sense amplifiers may be configurable based on the type of data being read. A Flash Security Measure is used to protect a protected memory area. A Flash Security Key is used for authentication and authorization a particular memory area. A XCAM (e.g., CAM) array is included in the Unified Memory. Unified Memory Concurrency is included.

Abstract: An array of floating gate memory cells, and a method of making same, where each pair of memory cells includes a pair of trenches formed into a surface of a semiconductor substrate, with a strip of the substrate disposed therebetween, a source region formed in the substrate strip, a pair of drain regions, a pair of channel regions each extending between the source region and one of the drain regions, a pair of floating gates each disposed in one of the trenches, and a pair of control gates. Each channel region has a first portion disposed in the substrate strip and extending along one of the trenches, a second portion extending underneath the one trench, a third portion extending along the one trench, and a fourth portion extending along the substrate surface and under one of the control gates.