Patents by Inventor Hiroaki Ammo

Hiroaki Ammo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10163776
    Abstract: Disclosed herein is a capacitive element formed by multilayer wirings, wherein a total capacitance, intralayer capacitance and interlayer capacitance are calculated for a plurality of device structures by changing parameters relating to the multilayer wirings in an integrated circuit, a device structure is identified, from among the plurality of device structures, whose difference in the total capacitance between the device structures is equal to or less than a predetermined level and at least either of whose ratio of the intralayer capacitance to the total capacitance or ratio of the interlayer capacitance to the total capacitance satisfies a predetermined condition, and the parameters of the device structure satisfying the predetermined condition are determined as the parameters of the multilayer wirings.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: December 25, 2018
    Assignee: Sony Corporation
    Inventors: Kyoko Izuha, Hiroaki Ammo, Yoshiyuki Enomoto
  • Publication number: 20180343408
    Abstract: The present technique relates to a solid-state imaging device, a solid-state imaging device manufacturing method, and an electronic apparatus that are capable of providing a solid-state imaging device that can prevent generation of RTS noise due to miniaturization of amplifying transistors, and can achieve a smaller size and a higher degree of integration accordingly. A solid-state imaging device (1-1) includes: a photodiode (PD) as a photoelectric conversion unit; a transfer gate (TG) that reads out charges from the photodiode (PD); a floating diffusion (FD) from which the charges of the photodiode (PD) are read by an operation of the transfer gate (TG); and an amplifying transistor (Tr3) connected to the floating diffusion (FD). More particularly, the amplifying transistor (Tr3) is of a fully-depleted type.
    Type: Application
    Filed: August 6, 2018
    Publication date: November 29, 2018
    Inventor: HIROAKI AMMO
  • Publication number: 20180337791
    Abstract: The present disclosure relates to a signal processing circuit and method for the same capable of generating a stable physical unclonable function (PUF) being less susceptible to environmental changes and having less characteristic deterioration. Two VDDs are voltages alternately inverted. The two VDDs perform charge and discharge such that one is turned on while the other is turned off, and a current flows by a difference at an edge during switching (inversion). The output I1 is proportional to a capacitance value difference between the pair of DUTs, and the capacitance value difference between the pair of DUTs can be obtained by ?C=?I/(VDD*f). The present technology is applicable to a signal processing circuit on which a differential pair is mounted, for example.
    Type: Application
    Filed: November 2, 2016
    Publication date: November 22, 2018
    Inventors: HIROAKI AMMO, KEN SAWADA
  • Patent number: 10044962
    Abstract: The present technique relates to a solid-state imaging device, a solid-state imaging device manufacturing method, and an electronic apparatus that are capable of providing a solid-state imaging device that can prevent generation of RTS noise due to miniaturization of amplifying transistors, and can achieve a smaller size and a higher degree of integration accordingly. A solid-state imaging device (1-1) includes: a photodiode (PD) as a photoelectric conversion unit; a transfer gate (TG) that reads out charges from the photodiode (PD); a floating diffusion (FD) from which the charges of the photodiode (PD) are read by an operation of the transfer gate (TG); and an amplifying transistor (Tr3) connected to the floating diffusion (FD). More particularly, the amplifying transistor (Tr3) is of a fully-depleted type.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: August 7, 2018
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Hiroaki Ammo
  • Patent number: 9912891
    Abstract: The present technique relates to a solid-state imaging device, a solid-state imaging device manufacturing method, and an electronic apparatus that are capable of providing a solid-state imaging device that can prevent generation of RTS noise due to miniaturization of amplifying transistors, and can achieve a smaller size and a higher degree of integration accordingly. A solid-state imaging device (1-1) includes: a photodiode (PD) as a photoelectric conversion unit; a transfer gate (TG) that reads out charges from the photodiode (PD); a floating diffusion (FD) from which the charges of the photodiode (PD) are read by an operation of the transfer gate (TG); and an amplifying transistor (Tr3) connected to the floating diffusion (FD). More particularly, the amplifying transistor (Tr3) is of a fully-depleted type.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: March 6, 2018
    Assignee: SONY CORPORATION
    Inventor: Hiroaki Ammo
  • Publication number: 20180053802
    Abstract: The present technique relates to a semiconductor device and an electronic appliance in which the reliability of the fine transistor can be maintained while the signal output characteristic is improved in a device formed by stacking semiconductor substrates.
    Type: Application
    Filed: October 16, 2017
    Publication date: February 22, 2018
    Inventors: Koichi BABA, Takashi KUBODERA, Toshihiko MIYAZAKI, Hiroaki AMMO
  • Publication number: 20180027200
    Abstract: The present technique relates to a solid-state imaging device, a solid-state imaging device manufacturing method, and an electronic apparatus that are capable of providing a solid-state imaging device that can prevent generation of RTS noise due to miniaturization of amplifying transistors, and can achieve a smaller size and a higher degree of integration accordingly. A solid-state imaging device (1-1) includes: a photodiode (PD) as a photoelectric conversion unit; a transfer gate (TG) that reads out charges from the photodiode (PD); a floating diffusion (FD) from which the charges of the photodiode (PD) are read by an operation of the transfer gate (TG); and an amplifying transistor (Tr3) connected to the floating diffusion (FD). More particularly, the amplifying transistor (Tr3) is of a fully-depleted type.
    Type: Application
    Filed: August 8, 2017
    Publication date: January 25, 2018
    Inventor: HIROAKI AMMO
  • Publication number: 20170339357
    Abstract: The present technique relates to a solid-state imaging device, a solid-state imaging device manufacturing method, and an electronic apparatus that are capable of providing a solid-state imaging device that can prevent generation of RTS noise due to miniaturization of amplifying transistors, and can achieve a smaller size and a higher degree of integration accordingly. A solid-state imaging device (1-1) includes: a photodiode (PD) as a photoelectric conversion unit; a transfer gate (TG) that reads out charges from the photodiode (PD); a floating diffusion (FD) from which the charges of the photodiode (PD) are read by an operation of the transfer gate (TG); and an amplifying transistor (Tr3) connected to the floating diffusion (FD). More particularly, the amplifying transistor (Tr3) is of a fully-depleted type.
    Type: Application
    Filed: August 8, 2017
    Publication date: November 23, 2017
    Inventor: HIROAKI AMMO
  • Patent number: 9818784
    Abstract: The present technique relates to a semiconductor device and an electronic appliance in which the reliability of the fine transistor can be maintained while the signal output characteristic is improved in a device formed by stacking semiconductor substrates.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: November 14, 2017
    Assignee: Sony Corporation
    Inventors: Koichi Baba, Takashi Kubodera, Toshihiko Miyazaki, Hiroaki Ammo
  • Patent number: 9762832
    Abstract: The present technique relates to a solid-state imaging device, a solid-state imaging device manufacturing method, and an electronic apparatus that are capable of providing a solid-state imaging device that can prevent generation of RTS noise due to miniaturization of amplifying transistors, and can achieve a smaller size and a higher degree of integration accordingly. A solid-state imaging device (1-1) includes: a photodiode (PD) as a photoelectric conversion unit; a transfer gate (TG) that reads out charges from the photodiode (PD); a floating diffusion (FD) from which the charges of the photodiode (PD) are read by an operation of the transfer gate (TG); and an amplifying transistor (Tr3) connected to the floating diffusion (FD). More particularly, the amplifying transistor (Tr3) is of a fully-depleted type.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: September 12, 2017
    Assignee: SONY CORPORATION
    Inventor: Hiroaki Ammo
  • Publication number: 20160248998
    Abstract: The present technique relates to a solid-state imaging device, a solid-state imaging device manufacturing method, and an electronic apparatus that are capable of providing a solid-state imaging device that can prevent generation of RTS noise due to miniaturization of amplifying transistors, and can achieve a smaller size and a higher degree of integration accordingly. A solid-state imaging device (1-1) includes: a photodiode (PD) as a photoelectric conversion unit; a transfer gate (TG) that reads out charges from the photodiode (PD); a floating diffusion (FD) from which the charges of the photodiode (PD) are read by an operation of the transfer gate (TG); and an amplifying transistor (Tr3) connected to the floating diffusion (FD). More particularly, the amplifying transistor (Tr3) is of a fully-depleted type.
    Type: Application
    Filed: May 4, 2016
    Publication date: August 25, 2016
    Inventor: HIROAKI AMMO
  • Publication number: 20160247851
    Abstract: The present technique relates to a semiconductor device and an electronic appliance in which the reliability of the fine transistor can be maintained while the signal output characteristic is improved in a device formed by stacking semiconductor substrates.
    Type: Application
    Filed: May 4, 2016
    Publication date: August 25, 2016
    Inventors: Koichi BABA, Takashi KUBODERA, Toshihiko MIYAZAKI, Hiroaki AMMO
  • Patent number: 9363451
    Abstract: The present technique relates to a solid-state imaging device, a solid-state imaging device manufacturing method, and an electronic apparatus that are capable of providing a solid-state imaging device that can prevent generation of RTS noise due to miniaturization of amplifying transistors, and can achieve a smaller size and a higher degree of integration accordingly. A solid-state imaging device (1-1) includes: a photodiode (PD) as a photoelectric conversion unit; a transfer gate (TG) that reads out charges from the photodiode (PD); a floating diffusion (FD) from which the charges of the photodiode (PD) are read by an operation of the transfer gate (TG); and an amplifying transistor (Tr3) connected to the floating diffusion (FD). More particularly, the amplifying transistor (Tr3) is of a fully-depleted type.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: June 7, 2016
    Assignee: SONY CORPORATION
    Inventor: Hiroaki Ammo
  • Patent number: 9362325
    Abstract: The present technique relates to a semiconductor device and an electronic appliance in which the reliability of the fine transistor can be maintained while the signal output characteristic is improved in a device formed by stacking semiconductor substrates.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: June 7, 2016
    Assignee: Sony Corporation
    Inventors: Koichi Baba, Takashi Kubodera, Toshihiko Miyazaki, Hiroaki Ammo
  • Publication number: 20150221694
    Abstract: The present technique relates to a semiconductor device and an electronic appliance in which the reliability of the fine transistor can be maintained while the signal output characteristic is improved in a device formed by stacking semiconductor substrates.
    Type: Application
    Filed: September 19, 2013
    Publication date: August 6, 2015
    Inventors: Koichi Baba, Takashi Kubodera, Toshihiko Miyazaki, Hiroaki Ammo
  • Publication number: 20150008525
    Abstract: A semiconductor device includes: a substrate; an insulator layer provided on the substrate; a first transistor provided on the insulator layer; a semiconductor layer including a plurality of impurity regions of a first conduction type, the impurity regions forming a part of the first transistor; a heat dissipation layer; a thermal conductive layer linking the semiconductor layer and the heat dissipation layer; and an interruption structure configured to interrupt a flow of a current between the first transistor and the thermal conductive layer.
    Type: Application
    Filed: June 20, 2014
    Publication date: January 8, 2015
    Inventors: Yuzo Fukuzaki, Hiroaki Ammo
  • Publication number: 20140327059
    Abstract: The present technique relates to a solid-state imaging device, a solid-state imaging device manufacturing method, and an electronic apparatus that are capable of providing a solid-state imaging device that can prevent generation of RTS noise due to miniaturization of amplifying transistors, and can achieve a smaller size and a higher degree of integration accordingly. A solid-state imaging device (1-1) includes: a photodiode (PD) as a photoelectric conversion unit; a transfer gate (TG) that reads out charges from the photodiode (PD); a floating diffusion (FD) from which the charges of the photodiode (PD) are read by an operation of the transfer gate (TG); and an amplifying transistor (Tr3) connected to the floating diffusion (FD). More particularly, the amplifying transistor (Tr3) is of a fully-depleted type.
    Type: Application
    Filed: December 7, 2012
    Publication date: November 6, 2014
    Inventor: Hiroaki Ammo
  • Patent number: 8178933
    Abstract: A semiconductor device including first and second transistors, each of the first and second transistors being formed with a plurality of fin transistors, and the first and second transistors being connected in parallel to electrically share a source, wherein the plurality of fin transistors each include a fin activation layer, the fin activation layer protruding from a semiconductor substrate, a source layer serving as the source being formed on one end, and a drain layer on the other end of the fin activation layer so as to form a channel region, the fin activation layers are arranged adjacent to each other in parallel, and the drain layers are disposed so that the currents flow through the plurality of fin transistors in opposite directions between the first and second transistors.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: May 15, 2012
    Assignee: Sony Corporation
    Inventors: Akira Mizumura, Hiroaki Ammo, Tetsuya Oishi
  • Publication number: 20110186932
    Abstract: A semiconductor device including first and second transistors, each of the first and second transistors being formed with a plurality of fin transistors, and the first and second transistors being connected in parallel to electrically share a source, wherein the plurality of fin transistors each include a fin activation layer, the fin activation layer protruding from a semiconductor substrate, a source layer serving as the source being formed on one end, and a drain layer on the other end of the fin activation layer so as to form a channel region, the fin activation layers are arranged adjacent to each other in parallel, and the drain layers are disposed so that the currents flow through the plurality of fin transistors in opposite directions between the first and second transistors.
    Type: Application
    Filed: March 3, 2011
    Publication date: August 4, 2011
    Applicant: SONY CORPORATION
    Inventors: Akira Mizumura, Hiroaki Ammo, Tetsuya Oishi
  • Patent number: 7932567
    Abstract: Disclosed herein is a semiconductor device including: first and second transistors, each of the first and second transistors being formed with a plurality of fin transistors, and the first and second transistors being connected in parallel to electrically share a source, wherein the plurality of fin transistors each include a fin activation layer, the fin activation layer protruding from a semiconductor substrate, a source layer serving as the source being formed on one end, and a drain layer on the other end of the fin activation layer so as to form a channel region, the fin activation layers are arranged adjacent to each other in parallel, and the drain layers are disposed so that the currents flow through the plurality of fin transistors in opposite directions between the first and second transistors.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: April 26, 2011
    Assignee: Sony Corporation
    Inventors: Akira Mizumura, Hiroaki Ammo, Tetsuya Oishi