Abstract: Disclosed herein is a capacitive element formed by multilayer wirings, wherein a total capacitance, intralayer capacitance and interlayer capacitance are calculated for a plurality of device structures by changing parameters relating to the multilayer wirings in an integrated circuit, a device structure is identified, from among the plurality of device structures, whose difference in the total capacitance between the device structures is equal to or less than a predetermined level and at least either of whose ratio of the intralayer capacitance to the total capacitance or ratio of the interlayer capacitance to the total capacitance satisfies a predetermined condition, and the parameters of the device structure satisfying the predetermined condition are determined as the parameters of the multilayer wirings.

Abstract: Disclosed herein is a semiconductor device including: first and second transistors, each of the first and second transistors being formed with a plurality of fin transistors, and the first and second transistors being connected in parallel to electrically share a source, wherein the plurality of fin transistors each include a fin activation layer, the fin activation layer protruding from a semiconductor substrate, a source layer serving as the source being formed on one end, and a drain layer on the other end of the fin activation layer so as to form a channel region, the fin activation layers are arranged adjacent to each other in parallel, and the drain layers are disposed so that the currents flow through the plurality of fin transistors in opposite directions between the first and second transistors.

Abstract: In a semiconductor device comprising a first bipolar transistor and a second bipolar transistor having different voltages formed on a semiconductor substrate made by forming an epitaxial layer on a silicon substrate, in an upper part of the silicon substrate the first bipolar transistor has an N+-type first embedded diffusion layer having an impurity concentration higher than that of the epitaxial layer and the second bipolar transistor has an N-type second embedded diffusion layer having a lower impurity concentration and a deeper diffusion layer depth than the first embedded diffusion layer, whereby a high speed bipolar transistor and a high voltage bipolar transistor are formed on the same substrate.

Abstract: A semiconductor device causes less element characteristic fluctuation and hardly causes parasitic actions even when a wire having a barrier metal made of a titanium material is provided. The semiconductor device includes a MOS transistor provided on the surface side of a semiconductor substrate, a first silicon oxide film, a silicon nitride film and a second silicon oxide film provided on the semiconductor substrate while covering the MOS transistor, and a wire having a barrier metal made of titanium material and provided on the insulating film, wherein the silicon nitride film covers the MOS transistor and has an opening on an element isolating region for isolating the MOS transistors. The silicon nitride film is formed in one and the same process as that of a dielectric film of a capacitor element.

Abstract: There is provided a semiconductor device which causes less element characteristic fluctuation and hardly causes parasitic actions even when a wire comprising a barrier metal made of a titanium material is provided. The semiconductor device comprises a MOS transistor provided on the surface side of a semiconductor substrate, a first silicon oxide film, a silicon nitride film-and a second silicon oxide film-provided on the semiconductor substrate while covering the MOS transistor and a wire having a barrier metal made of a titanium material and provided on the insulating film, and is characterized in that the silicon nitride film covers the MOS transistor and has an opening on an element isolating region for isolating the MOS transistors. The silicon nitride film may be what is formed in one and same process with that of a dielectric film of a capacitor element.

Abstract: Disclosed is a method of fabricating a semiconductor device in which at least an LDD type insulated-gate field effect transistor and a bipolar transistor are formed on a common base substrate. An insulating layer for forming side walls of an LDD type insulated-gate field effect transistor is formed by a stack of first and second insulating films. An opening is formed in the lower first insulating film at a position in a bipolar transistor forming area, and a single crystal semiconductor layer is formed on a base substrate through the opening. With this configuration, the fabrication steps can be simplified and the reliability of the semiconductor device can be enhanced.

Abstract: A method of producing a semiconductor device by which the resistivities of the base, collector, and source/drain regions in a Bi-CMOS are decreased and the production step is simplified. A method of producing a semiconductor device comprising the steps of forming a gate electrode (the first semiconductor layer) on a substrate; forming an insulating film; forming a second semiconductor layer; leaving the second semiconductor layer and the insulating film on the bipolar part and removing them on the CMOS part to form sidewalls on the side faces of the gate electrode; forming source/drain regions; forming a Ti layer over the entire surface and forming silicide on the surfaces of the second semiconductor layer, the source/drain regions, and the gate electrode; and forming a base electrode by patterning the second semiconductor layer.

Abstract: A high-resistance polycrystalline Si resistor having a stable resistance value even when micro-sized and a low-resistance polycrystalline Si resistor having a sufficiently low desired resistance value wherein a polycrystalline Si film is formed on an insulation film located on a Si substrate, high-resistance-making ion implantation is applied to the entire surface and medium-resistance-making ion implantation is selectively applied to a medium-resistance-making region of the polycrystalline Si film. Low-resistance-making ion implantation is selectively applied to a low-resistance-making region of the polycrystalline Si film. The product is annealed to grow the polycrystalline Si film by solid-phase growth, the film is patterned to form a high-resistance polycrystalline Si resistor, medium-resistance polycrystalline Si resistor, and low-resistance polycrystalline Si resistor.

Abstract: Disclosed is a method of fabricating a semiconductor device for preventing occurrence of an inconvenience due to exposure of a high melting point metal based material, for example, contamination of a chamber atmosphere due to the metal material upon formation of a semiconductor layer in an opening portion by selective epitaxial growth or upon pre-treatment thereof, to reduce occurrence of crystal defects or the like, thereby forming semiconductor devices at a high yield. The method includes the steps of: forming a conductive layer including a high melting point metal based material on a substrate; forming an opening portion in the conductive layer; covering the high melting point metal based material with a film; and forming a semiconductor layer on a portion of the substrate exposed in the opening portion by epitaxial growth after the step of covering the high melting point metal based material with the film.

Abstract: A semiconductor device comprises: a substrate; a first buried layer of a first conduction type formed in the substrate; a second buried layer of the first conduction type formed in the substrate; a third buried layer of the first conduction type formed in the substrate; an epitaxial layer of the first conduction type formed on the substrate; a well region of a second conduction type formed in the epitaxial layer above the third buried layer; source/drain regions of the first conduction type formed in the well region; a first base region of the second conduction type formed in the epitaxial layer above the first buried layer; a first impurity region of the first conduction type formed on the first base region; a second base region of the second conduction type formed in the epitaxial layer above the second buried layer; a second impurity region of the first conduction type formed on the second base region; a first lead-out layer of the first conduction type connected to the first buried layer; and a second lea

Abstract: A bipolar semiconductor device includes an npn transistor using a base outlet electrode in the form of a polycrystalline Si film and one or more other devices using an electrode in the form of a polycrystalline Si film supported on a common p-type Si substrate, the sheet resistance of the polycrystalline Si film forming the base outlet electrode of the npn transistor is decreased to two thirds of the sheet resistance of the polycrystalline Si film forming at least one electrode of at least one other device. The base outlet electrode can be made by first making the polycrystalline Si film on the entire surface of the substrate, then applying selective ion implantation of Si to a selective portion of the polycrystalline Si film for making the base outlet electrode to change it into an amorphous state, and then annealing the product to grow the polycrystalline Si film by solid-phase growth.

Abstract: In a semiconductor device comprising a first bipolar transistor and a second bipolar transistor having different voltages formed on a semiconductor substrate made by forming an epitaxial layer on a silicon substrate, in an upper part of the silicon substrate the first bipolar transistor has an N.sup.+ -type first embedded diffusion layer having an impurity concentration higher than that of the epitaxial layer and the second bipolar transistor has an N-type second embedded diffusion layer having a lower impurity concentration and a deeper diffusion layer depth than the first embedded diffusion layer, whereby a high speed bipolar transistor and a high voltage bipolar transistor are formed on the same substrate.

Abstract: A process for forming a first bipolar transistor having a single polysilicon structure and a second bipolar transistor having a single polysilicon structure and being of a conducting type opposite to that of the first bipolar transistor on the same substrate. In the process of fabricating a semiconductor device in which a first bipolar transistor having a single polysilicon structure, a second bipolar transistor having a single polysilicon structure and being of a conducting type opposite to that of the first bipolar transistor, and a third bipolar transistor having a double polysilicon structure are provided on the same semiconductor substrate, a base contact portion of the first bipolar transistor and an emitter of the second bipolar transistor are formed in the same step, and an emitter of the first bipolar transistor and base contact portions of the second and third bipolar transistors are formed in the same step.

Abstract: A high-resistance polycrystalline Si resistor having a stable resistance value even when micro-sized and a low-resistance polycrystalline Si resistor having a sufficiently low desired resistance value wherein a polycrystalline Si film is formed on an insulation film located on a Si substrate, high-resistance-making ion implantation is applied to the entire surface and medium-resistance-making ion implantation is selectively applied to a medium-resistance-making region of the polycrystalline Si film. Low-resistance-making ion implantation is selectively applied to a low-resistance-making region of the polycrystalline Si film. The product is annealed to grow the polycrystalline Si film by solid-phase growth, the film is patterned to form a high-resistance polycrystalline Si resistor, medium-resistance polycrystalline Si resistor, and low-resistance polycrystalline Si resistor.

Abstract: A method of producing a bipolar transistor includes the step of forming an emitter contact layer containing a high concentration of impurity by means of plasma doping or solid-state diffusion without causing diffusion of impurity in a base layer. This makes it possible to realize a thin base layer having a high impurity concentration.The invention also provides a method of producing a semiconductor device including a bipolar transistor and another device element such as a resistor element including a polysilicon layer containing an activated impurity in such a manner that both the bipolar transistor and the device element are disposed on the same single substrate, the method including the steps of: forming a polysilicon layer containing an activated impurity on the surface of a substrate; and then forming a base layer of the bipolar transistor. This method prevents the base layer from being affected by heat treatment on the polysilicon layer.

Abstract: To form NPN and PNP transistors on the same base for example to obtain a complementary bipolar transistor it has been necessary to make an epitaxial layer a thick film, and this has resulted in deterioration of the characteristics of the NPN transistor. Also, because a step of forming an alignment mark has been necessary this has increased the number of manufacturing steps needed to make a complementary bipolar transistor. This invention provides a semiconductor device manufacturing method which solves this problem as follows: After a first opening 13 (alignment mark 16) and a second opening 14 are formed in an insulating film 12 formed on a semiconductor base 11 and a doping mask 15 is then formed on the semiconductor base 11, a third opening 17 is formed thereon with the alignment mark 16 as a reference.