Abstract: A semiconductor device includes a layer having first and second surfaces, a first region including central and peripheral portions, and a second region on the first region. First trenches extend into the first surface and terminate within the first region in the central portion. Each first trench includes a first electrode and a gate electrode over the first electrode. The first and gate electrodes are spaced from the first and second regions by a first insulating layer. A second trench extends into the first surface and terminates within the first region in the peripheral portion. The second trench includes a second electrode and a third electrode over the second electrode. The second and third electrodes are spaced from the first and second regions by a second insulating layer. A fourth electrode overlies the first insulating layer in the central portion and the second insulating layer in the peripheral portion.

Abstract: A semiconductor device includes a layer having first and second surfaces, a first region including central and peripheral portions, and a second region on the first region. First trenches extend into the first surface and terminate within the first region in the central portion. Each first trench includes a first electrode and a gate electrode over the first electrode. The first and gate electrodes are spaced from the first and second regions by a first insulating layer. A second trench extends into the first surface and terminates within the first region in the peripheral portion. The second trench includes a second electrode and a third electrode over the second electrode. The second and third electrodes are spaced from the first and second regions by a second insulating layer. A fourth electrode overlies the first insulating layer in the central portion and the second insulating layer in the peripheral portion.

Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided on a part of the first semiconductor region, a third semiconductor region of the first conductivity type provided on a part of the second semiconductor region, agate electrode, a first electrode, and a conductive portion. The gate electrode is provided on another part of the second semiconductor region via a gate insulating portion. The first electrode is provided on the third semiconductor region and electrically connected to the third semiconductor region. The conductive portion is provided on another part of the first semiconductor region via a first insulating portion and electrically connected to the first electrode, and includes a portion arranged side by side with the gate electrode in a second direction perpendicular to a first direction from the first semiconductor region to the first electrode.

Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a conductive layer, a gate electrode, and a first electrode. The conductive layer includes a first portion, a second portion, and a third portion. The first portion is surrounded by the first semiconductor region via a first insulating portion. The second portion extends in a second direction, is provided on the first semiconductor region, and is provided on the second region. The third portion is connected between the first portion and the second portion and extends in a third direction. The first electrode is electrically connected to the third semiconductor region and the conductive layer. The second portion electrically connects the first electrode to the third portion.

Abstract: The generation of a variation in properties of vertical transistors is restrained. A vertical MOS transistor is formed in a semiconductor substrate. A first interlayer dielectric film and a first source wiring are formed over the front surface of the substrate. The first source wiring is formed over the first interlayer dielectric film, and is overlapped with the vertical MOS transistor as viewed in plan. Contacts are buried in the first interlayer dielectric film. Through the contacts, an n-type source layer of vertical MOS transistor is coupled with the first source wiring. Openings are made in the first source wiring.

Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a conductive layer, a gate electrode, and a first electrode. The conductive layer includes a first portion, a second portion, and a third portion. The first portion is surrounded by the first semiconductor region via a first insulating portion. The second portion extends in a second direction, is provided on the first semiconductor region, and is provided on the second region. The third portion is connected between the first portion and the second portion and extends in a third direction. The first electrode is electrically connected to the third semiconductor region and the conductive layer. The second portion electrically connects the first electrode to the third portion.

Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type, each comprising a first part, on the first semiconductor region, wherein the second semiconductor regions are spaced apart in a first direction, a third semiconductor region of the first conductivity type on each of the second semiconductor regions, an insulation portion between two of the second semiconductor regions, the insulation portion having one side in contact with one of the first parts and the other side in contact with one of the third semiconductor regions, a first electrode within the insulation portion, a gate electrode spaced apart from the first electrode and within the insulation portion, and a second electrode on the third semiconductor region and electrically connected to the first electrode and the third semiconductor region.

Abstract: According to one embodiment, a semiconductor device comprises a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a gate interconnect, a second insulating layer, and a first electrode. The first semiconductor region includes a first region and a second region provided around the first region. The gate interconnect is provided on the second region. The gate interconnect includes a first portion and a second portion provided around the second portion. A thickness in the first direction of the second portion is thinner than a thickness in the first direction of the first portion. A length in the second direction of the gate interconnect is longer than a length in the third direction of the gate electrode. The first electrode contacts the gate interconnect.

Abstract: According to one embodiment, a semiconductor device comprises a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a gate interconnect, a second insulating layer, and a first electrode. The first semiconductor region includes a first region and a second region provided around the first region. The gate interconnect is provided on the second region. The gate interconnect includes a first portion and a second portion provided around the second portion. A thickness in the first direction of the second portion is thinner than a thickness in the first direction of the first portion. A length in the second direction of the gate interconnect is longer than a length in the third direction of the gate electrode. The first electrode contacts the gate interconnect.

Abstract: A method for manufacturing a semiconductor device, includes forming a recess over a surface of an n-type semiconductor substrate, forming a gate insulation film over an inner wall and a bottom face of the recess, embedding a gate electrode into the recess, forming a p-type base layer in a surface layer of the semiconductor substrate so as to be shallower than the recess, and forming an n-type source layer in the p-type base layer so as to be shallower than the p-type base layer. An impurity profile of the p-type base layer in a thickness direction includes a first peak, a second peak being located closer to a bottom face side of the semiconductor substrate than the first peak and being higher than the first peak, and a third peak located between the first peak and the second peak by implanting impurity ions three times or more at ion implantation energies different from each other in the forming of the p-type base layer.

Abstract: Trenches are formed in a base layer and extend parallel to each other. A gate insulating film is formed on the inner wall of each of multiple trenches. A gate electrode GE is buried in each of the trenches. The source layer is formed in the base layer to a depth less than the base layer. The source layer is disposed between each of the trenches. A second conduction type high concentration layer is formed between the source layer and the trench in a plan view. The trench, the source layer, and the second conduction type high concentration are arranged in this order repetitively in a plan view. One lateral side of the trench faces the source layer and the other lateral side of the trench faces the second conduction type high concentration layer.

Abstract: Trenches are formed in a base layer and extend parallel to each other. A gate insulating film is formed on the inner wall of each of multiple trenches. A gate electrode GE is buried in each of the trenches. The source layer is formed in the base layer to a depth less than the base layer. The source layer is disposed between each of the trenches. A second conduction type high concentration layer is formed between the source layer and the trench in a plan view. The trench, the source layer, and the second conduction type high concentration are arranged in this order repetitively in a plan view. One lateral side of the trench faces the source layer and the other lateral side of the trench faces the second conduction type high concentration layer.

Abstract: A method for manufacturing a semiconductor device, includes forming a recess over a surface of an n-type semiconductor substrate, forming a gate insulation film over an inner wall and a bottom face of the recess, embedding a gate electrode into the recess, forming a p-type base layer in a surface layer of the semiconductor substrate so as to be shallower than the recess, and forming an n-type source layer in the p-type base layer so as to be shallower than the p-type base layer. An impurity profile of the p-type base layer in a thickness direction includes a first peak, a second peak being located closer to a bottom face side of the semiconductor substrate than the first peak and being higher than the first peak, and a third peak located between the first peak and the second peak by implanting impurity ions three times or more at ion implantation energies different from each other in the forming of the p-type base layer.

Abstract: A semiconductor device includes a base region of a second conduction type provided over a drain region of a first conduction type, an outer peripheral well region of a second conduction type provided to cover the outer peripheral end of the base region and having an impurity concentration lower than that of the base region, a buried electrode buried in the semiconductor substrate not to overlap the outer peripheral well region, plural gate electrodes connected to the buried electrode and buried in the substrate such that each of them is adjacent to a source region, a gate interconnect provided over the substrate to overlap a portion of the outer peripheral well region in a plan view and connected to the buried electrode, and a grounding electrode provided over the substrate and connected to a portion of the outer peripheral well region not overlapping the gate interconnect in a plan view.

Abstract: A method for manufacturing a semiconductor device includes forming a recess over a surface of an n-type semiconductor substrate, forming a gate insulation film over an inner wall and a bottom face of the recess, embedding a gate electrode into the recess, forming a p-type base layer in the surface layer of the substrate so as to be shallower than the recess; and forming an n-type source layer in the p-type base layer so as to be shallower than the p-type base layer. The impurity profile of the p-type base layer in a thickness direction includes a second peak being located closer to a bottom face side of the substrate than the first peak and being higher than the first peak, and a third peak located between the first peak and the second peak by implanting impurity ions three times or more at ion implantation energies different from each other.

Abstract: A display apparatus is configured so that, between a first substrate and a second substrate, a first spacer member disposed along an edge of an outer main surface of the first substrate at one side of an outer region of a circuit board on an extension of a disposition direction of a plurality of electrode terminals and a second spacer member disposed along the edge of the outer main surface of the first substrate at the other side of the outer region are disposed.

Abstract: A semiconductor device includes a base region of a second conduction type provided over a drain region of a first conduction type, an outer peripheral well region of a second conduction type provided to cover the outer peripheral end of the base region and having an impurity concentration lower than that of the base region, a buried electrode buried in the semiconductor substrate not to overlap the outer peripheral well region, plural gate electrodes connected to the buried electrode and buried in the substrate such that each of them is adjacent to a source region, a gate interconnect provided over the substrate to overlap a portion of the outer peripheral well region in a plan view and connected to the buried electrode, and a grounding electrode provided over the substrate and connected to a portion of the outer peripheral well region not overlapping the gate interconnect in a plan view.

Abstract: The generation of a variation in properties of vertical transistors is restrained. A vertical MOS transistor is formed in a semiconductor substrate. A first interlayer dielectric film and a first source wiring are formed over the front surface of the substrate. The first source wiring is formed over the first interlayer dielectric film, and is overlapped with the vertical MOS transistor as viewed in plan. Contacts are buried in the first interlayer dielectric film. Through the contacts, an n-type source layer of vertical MOS transistor is coupled with the first source wiring. Openings are made in the first source wiring.

Abstract: A trench gate type MISFET and a diode are formed in a semiconductor substrate. First and second trenches are formed in the semiconductor substrate. A gate electrode is formed in the first trench through a gate insulating film. A dummy gate electrode is formed in the second trench through a dummy gate insulating film. A cathode n+-type semiconductor region and an anode p-type semiconductor region are formed in the semiconductor substrate and the second trench is formed so as to surround the n+-type semiconductor region in a planar view. A part of the anode p-type semiconductor region is formed directly below the n+-type semiconductor region, so that a PN junction is formed between the part of the anode p-type semiconductor region and the n+-type semiconductor region. Thereby a diode is formed. The dummy gate electrode is electrically coupled to one of an anode and a cathode.

Abstract: The generation of a variation in properties of vertical transistors is restrained. A vertical MOS transistor is formed in a semiconductor substrate. A first interlayer dielectric film and a first source wiring are formed over the front surface of the substrate. The first source wiring is formed over the first interlayer dielectric film, and is overlapped with the vertical MOS transistor as viewed in plan. Contacts are buried in the first interlayer dielectric film. Through the contacts, an n-type source layer of vertical MOS transistor is coupled with the first source wiring. Openings are made in the first source wiring.