Abstract: Two load lock chambers having a load lock pedestal are provided adjacent to a vacuum process chamber through a vacuum intermediate chamber. A passage opening is provided between the vacuum process chamber and the vacuum intermediate chamber. Two wafer retaining arms are installed between a platen device in the vacuum process chamber and the vacuum intermediate chamber. The two wafer retaining arms are reciprocatingly movable between the corresponding load lock pedestals and the platen device while passing through the passage opening and crossing with an overpass each other at different levels. By retaining an unprocessed wafer by one of the wafer retaining arms and retaining a processed wafer by the other wafer retaining arm, transfer of the unprocessed wafer from one of the load lock pedestals to the platen device and transfer of the processed wafer from the platen device to the other load lock pedestal are performed simultaneously.

Abstract: Two load lock chambers having a load lock pedestal are provided adjacent to a vacuum process chamber through a vacuum intermediate chamber. A passage opening is provided between the vacuum process chamber and the vacuum intermediate chamber. Two wafer retaining arms are installed between a platen device in the vacuum process chamber and the vacuum intermediate chamber. The two wafer retaining arms are reciprocatingly movable between the corresponding load lock pedestals and the platen device while passing through the passage opening and crossing with an overpass each other at different levels. By retaining an unprocessed wafer by one of the wafer retaining arms and retaining a processed wafer by the other wafer retaining arm, transfer of the unprocessed wafer from one of the load lock pedestals to the platen device and transfer of the processed wafer from the platen device to the other load lock pedestal are performed simultaneously.

Abstract: As first thermal treatment for activating an impurity injected into a gate electrode, thermal treatment at a low temperature for a long time in which boron diffusion into each crystal grain in polysilicon hardly occurs and boron diffusion in each crystal boundary occurs is performed. Next, as second thermal treatment, thermal treatment at a high temperature for a short time, such as spike annealing and flash annealing, in which impurity diffusion into each crystal grain in a polysilicon layer occurs is performed.

Abstract: With keeping an atmosphere including oxygen within a chamber and with a wafer kept at a low temperature, plasma generated within the chamber is biased toward the wafer, and the wafer is subjected to the plasma. A semiconductor layer exposed on the wafer is oxidized into an oxide film. Thus, an oxide film can be formed even at room temperature differently from thermal oxidation. This oxidation is applicable to recovery of an implantation protection insulating film having been etched in cleaning a photoresist film, relaxation of a step formed between polysilicon films, relaxation of a step formed within a trench and the like. Also, before removing a photoresist film used for forming a gate electrode including a metal, a contamination protection film can be formed by this oxidation with the photoresist film kept.

Abstract: Impurities for threshold voltage adjustment are implanted using a resist film and a protective dielectric as implantation masks from directions inclined at 10° through 30° with respect to the direction vertical to the principal surface of a semiconductor substrate 1 when viewed in cross section taken along the gate width direction. Thus, first low-concentration impurity implantation regions are formed to overlap each other in the central part of an active region for a memory cell MIS transistor Mtrs of an SRAM. Furthermore, after an isolation is formed, a second low-concentration impurity implantation region is formed in an active region for each of MIS transistors Ltr, Mtrs and Mtrl by implanting impurity ions without using implantation masks. The MIS transistors Ltr, Mtrs and Mtrl formed after the completion of the fabricating process have substantially the same threshold voltage.

Abstract: A memory cell transistor and a planar capacitor are provided in a memory region, and both transistors of a CMOS device are provided in a logic circuit region. A capacitance dielectric 15 and a plate electrode 16b of the planar capacitor are provided over a trench shared with a shallow trench isolation 12a, and the upper part of the trench is filled with the capacitance dielectric 15 and the plate electrode 16b. An n-type diffusion layer 19 that is a storage node is formed, with an end region thereof extending along one side of the upper part of the trench, to a region of the substrate overlapping with the shallow trench isolation 12a. The area of a part of the substrate functioning as a capacitor can be increased without increasing the substrate area.

Abstract: Semiconductor devices each having a semiconductor layer (1), a gate insulating film (2), a gate electrode (3), an offset spacer layer (4), and SD extension diffusion layers (6) into which ions have been implanted by using the gate electrode (3) and the offset spacer layer (4) as a mask are formed by varying the film thickness of the offset spacer layer (4) and leakage current values in the respective semiconductor devices are measured. The results of the measurements show that the film thickness value of the offset spacer layer (4) and the leakage current value have a correlation therebetween and that the film thickness value of the offset spacer layer (4) when the leakage current value becomes zero corresponds to the length of the portion of the semiconductor layer (1) extending from under the outer end of the offset spacer layer (4) to the tip end of an impurity diffusion layer.

Abstract: A silicon oxynitride film is formed on a substrate. Then, a heat treatment is performed, while keeping a surface of the silicon oxynitride film in contact with a gas containing nitrogen, such as an NO gas, to introduce at least nitrogen into the silicon oxynitride film and produce a steeply sloped distribution of nitrogen. A semiconductor film containing an impurity, such as an amorphous silicon film, is formed on the silicon oxynitride film. By forming a CMOS device with, in particular, a dual gate structure which comprises p-type and n-type MIS transistors each having a gate oxide film composed of the silicon oxynitride film and a gate electrode composed of a polysilicon film, a high driving force is provided, while boron penetration in the p-type MIS transistor is suppressed.

Abstract: A method for evaluating an insulating film includes: a first step of forming an insulating film on a semiconductor substrate including a p-n junction therein; a second step of selectively forming an electrode pattern on the insulating film; a third step of forming a measurement electrode on the insulating film so as to be electrically insulated from the electrode pattern; and a fourth step of applying a measurement voltage between the measurement electrode and the semiconductor substrate via the insulating film and measuring a leakage current leaking through the p-n junction so as to evaluate a damage to the insulating film or the semiconductor substrate.

Abstract: As first thermal treatment for activating an impurity injected into a gate electrode, thermal treatment at a low temperature for a long time in which boron diffusion into each crystal grain in polysilicon hardly occurs and boron diffusion in each crystal boundary occurs is performed. Next, as second thermal treatment, thermal treatment at a high temperature for a short time, such as spike annealing and flash annealing, in which impurity diffusion into each crystal grain in a polysilicon layer occurs is performed.

Abstract: After a first gate insulating film is formed on each of first to third active regions, the first gate insulating film on the second active region is removed therefrom and a second gate insulating film thinner than the first gate insulating film is formed on the second active region. Then, the first gate insulating film on the third active region is removed therefrom and a third gate insulating film thinner than the second gate insulating film is formed on the third active region. Otherwise, a pad oxide film on the first active region is removed therefrom and the first gate insulating film is formed on the first active region. Then, the pad oxide film on the second active region is removed therefrom and a second gate insulating film thinner than the first gate insulating film is formed on the second active region. Thereafter, the pad oxide film on the third active region is removed therefrom and a third gate insulating film thinner than the second gate insulating film is formed on the third active region.

Abstract: With keeping an atmosphere including oxygen within a chamber and with a wafer kept at a low temperature, plasma generated within the chamber is biased toward the wafer, and the wafer is subjected to the plasma. A semiconductor layer exposed on the wafer is oxidized into an oxide film. Thus, an oxide film can be formed even at room temperature differently from thermal oxidation. This oxidation is applicable to recovery of an implantation protection insulating film having been etched in cleaning a photoresist film, relaxation of a step formed between polysilicon films, relaxation of a step formed within a trench and the like. Also, before removing a photoresist film used for forming a gate electrode including a metal, a contamination protection film can be formed by this oxidation with the photoresist film kept.

Abstract: With keeping an atmosphere including oxygen within a chamber and with a wafer kept at a low temperature, plasma generated within the chamber is biased toward the wafer, and the wafer is subjected to the plasma. A semiconductor layer exposed on the wafer is oxidized into an oxide film. Thus, an oxide film can be formed even at room temperature differently from thermal oxidation. This oxidation is applicable to recovery of an implantation protection insulating film having been etched in cleaning a photoresist film, relaxation of a step formed between polysilicon films, relaxation of a step formed within trench and the like. Also, before removing a photoresist film used for forming a gate electrode including a metal, a contamination protection film can be formed by this oxidation with the photoresist film kept.

Abstract: Impurities for threshold voltage adjustment are implanted using a resist film and a protective dielectric as implantation masks from directions inclined at 10° through 30° with respect to the direction vertical to the principal surface of a semiconductor substrate 1 when viewed in cross section taken along the gate width direction. Thus, first low-concentration impurity implantation regions are formed to overlap each other in the central part of an active region for a memory cell MIS transistor Mtrs of an SRAM. Furthermore, after an isolation is formed, a second low-concentration impurity implantation region is formed in an active region for each of MIS transistors Ltr, Mtrs and Mtrl by implanting impurity ions without using implantation masks. The MIS transistors Ltr, Mtrs and Mtrl formed after the completion of the fabricating process have substantially the same threshold voltage.

Abstract: A semiconductor substrate and an impurity solid that comprises of impurity to be introduced to a diode formation region are held in a vacuum chamber. Inert or reactive gas is introduced into the vacuum chamber to generate plasma composed of the inert or reactive gas. A first voltage allowing the impurity solid to serve as a cathode for the plasma is applied to the said impurity solid and the said impurity solid is sputtered by ions in the plasma, thereby mixing the impurity within the said impurity solid into the plasma. A second voltage allowing a semiconductor substrate to serve as a cathode for the plasma is applied to the said semiconductor substrate, thereby directly introducing the impurity within the plasma to the surface portion of the diode formation region of the said semiconductor substrate, generating a impurity layer.

Abstract: In a silicon layer formed on an insulator layer, a lattice defect region is formed to be adjacent to a channel region and source/drain regions, and the lower part of the channel region functions as a high-concentration channel region. The holes of hole-electron pairs generated in the channel region are eliminated by recombination in the lattice defect region, thereby suppressing the bipolar operation resulting from the accumulation of holes and increasing the source/drain breakdown voltage. The threshold value of a parasitic transistor is increased by the high-concentration channel region so as to reduce the leakage current in the OFF state. Alternatively, the holes may be moved to the source region to disappear therein by providing, instead of the lattice defect region, a high-concentration diffusion layer constituting and operating as a pn diode between the channel and source regions.

Abstract: A memory cell transistor and a planar capacitor are provided in a memory region, and both transistors of a CMOS device are provided in a logic circuit region. A capacitance dielectric 15 and a plate electrode 16b of the planar capacitor are provided over a trench shared with a shallow trench isolation 12a, and the upper part of the trench is filled with the capacitance dielectric 15 and the plate electrode 16b. An n-type diffusion layer 19 that is a storage node is formed, with an end region thereof extending along one side of the upper part of the trench, to a region of the substrate overlapping with the shallow trench isolation 12a. The area of a part of the substrate functioning as a capacitor can be increased without increasing the substrate area.

Abstract: Semiconductor devices each having a semiconductor layer (1), a gate insulating film (2), a gate electrode (3), an offset spacer layer (4), and SD extension diffusion layers (6) into which ions have been implanted by using the gate electrode (3) and the offset spacer layer (4) as a mask are formed by varying the film thickness of the offset spacer layer (4) and leakage current values in the respective semiconductor devices are measured. The results of the measurements show that the film thickness value of the offset spacer layer (4) and the leakage current value have a correlation therebetween and that the film thickness value of the offset spacer layer (4) when the leakage current value becomes zero corresponds to the length of the portion of the semiconductor layer (1) extending from under the outer end of the offset spacer layer (4) to the tip end of an impurity diffusion layer.

Abstract: A semiconductor substrate and an impurity solid that comprises of impurity to be introduced to a diode formation region are held in a vacuum chamber. Inert or reactive gas is introduced into the vacuum chamber to generate plasma composed of the inert or reactive gas. A first voltage allowing the impurity solid to serve as a cathode for the plasma is applied to the said impurity solid and the said impurity solid is sputtered by ions in the plasma, thereby mixing the impurity within the said impurity solid into the plasma. A second voltage allowing a semiconductor substrate to serve as a cathode for the plasma is applied to the said semiconductor substrate, thereby directly introducing the impurity within the plasma to the surface portion of the diode formation region of the said semiconductor substrate, generating a impurity layer.

Abstract: After a first gate insulating film is formed on each of first to third active regions, the first gate insulating film on the second active region is removed therefrom and a second gate insulating film thinner than the first gate insulating film is formed on the second active region. Then, the first gate insulating film on the third active region is removed therefrom and a third gate insulating film thinner than the second gate insulating film is formed on the third active region. Otherwise, a pad oxide film on the first active region is removed therefrom and the first gate insulating film is formed on the first active region. Then, the pad oxide film on the second active region is removed therefrom and a second gate insulating film thinner than the first gate insulating film is formed on the second active region. Thereafter, the pad oxide film on the third active region is removed therefrom and a third gate insulating film thinner than the second gate insulating film is formed on the third active region.