Abstract: A method for evaluating an insulating film includes: a first step of forming an insulating film on a semiconductor substrate including a p-n junction therein; a second step of selectively forming an electrode pattern on the insulating film; a third step of forming a measurement electrode on the insulating film so as to be electrically insulated from the electrode pattern; and a fourth step of applying a measurement voltage between the measurement electrode and the semiconductor substrate via the insulating film and measuring a leakage current leaking through the p-n junction so as to evaluate a damage to the insulating film or the semiconductor substrate.

Abstract: In a silicon layer formed on an insulator layer, a lattice defect region is formed to be adjacent to a channel region and source/drain regions, and the lower part of the channel region functions as a high-concentration channel region. The holes of hole-electron pairs generated in the channel region are eliminated by recombination in the lattice defect region, thereby suppressing the bipolar operation resulting from the accumulation of holes and increasing the source/drain breakdown voltage. The threshold value of a parasitic transistor is increased by the high-concentration channel region so as to reduce the leakage current in the OFF state. Alternatively, the holes may be moved to the source region to disappear therein by providing, instead of the lattice defect region, a high-concentration diffusion layer constituting and operating as a pn diode between the channel and source regions.

Abstract: In a silicon layer formed on an insulator layer, a lattice defect region is formed to be adjacent to a channel region and source/drain regions, and the lower part of the channel region functions as a high-concentration channel region. The holes of hole-electron pairs generated in the channel region are eliminated by recombination in the lattice defect region, thereby suppressing the bipolar operation resulting from the accumulation of holes and increasing the source/drain breakdown voltage. The threshold value of a parasitic transistor is increased by the high-concentration channel region so as to reduce the leakage current in the OFF state. Alternatively, the holes may be moved to the source region to disappear therein by providing, instead of the lattice defect region, a high-concentration diffusion layer constituting and operating as a pn diode between the channel and source regions.

Abstract: A sample table for holding a silicon substrate into which an impurity is introduced is provided in the lower portion of a vacuum chamber. A high frequency power source is connected to the sample table through a coupling capacitor. The high frequency power source has a self-bias of 500 V, for example. Gas introducing means for introducing a sputtering gas such as an argon gas is provided on the bottom of the vacuum chamber. A solid target which contains an impurity which should be introduced, for example, boron is provided in the upper portion of the vacuum chamber.

Abstract: An impurity solid including boron as impurity and a solid sample to which boron is introduced are held in a vacuum chamber. Ar gas is introduced into the vacuum chamber to generate plasma composed of the Ar gas. A voltage allowing the impurity solid to serve as a cathode for the plasma is applied to the impurity solid and the impurity solid is sputtered by ions in the plasma, thereby mixing boron included in the impurity solid into the plasma composed of Ar gas. A voltage allowing the solid sample to serve as a cathode for the plasma is applied to the solid sample, and boron mixed into the plasma is introduced to the surface portion of the solid sample.

Abstract: In order to dope impurities selectively at low temperature where the resist can be used, the invention presents an impurity doping method capable of performing not only cleaning process but also doping process at low temperature where the resist can be used. First, the active sample surface of a solid sample is exposed by irradiation with plasma, and without active irradiation with plasma, the gas or vapor containing object impurities is contacted with the active sample surface of the solid sample to dope the impurities. As a result, the impurity doping process at the time of formation of C-MOS structure or the like can be executed at low temperature so as not to spoil the function of the resist.

Abstract: On a semiconductor substrate made of p-type silicon, there are formed, in a successively layered fashion, a first p-type silicon semiconductor layer, laterally paired first n-type silicon semiconductor layers, laterally paired second p-type silicon semiconductor layers, and laterally paired n-type silicon semiconductor layers, by an epitaxial growth method. On the second n-type silicon semiconductor layer on the right side, there are successively formed a third p-type silicon semiconductor layer, a third n-type silicon semiconductor layer and a fourth p-type silicon semiconductor layer. The left first n-type silicon semiconductor layer, left second p-type silicon semiconductor layer and left second n-type silicon semiconductor layer form a first insular multilayered portion forming an n-channel MOSFET. The third p-type silicon semiconductor layer, third n-type silicon semiconductor layer and fourth p-type silicon semiconductor layer form a second insular portion forming a p-channel MOSFET.

Abstract: Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

Abstract: Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment. P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

Abstract: On a semiconductor substrate made of p-type silicon, there are formed, in a successively layered fashion, a first p-type silicon semiconductor layer, laterally paired first n-type silicon semiconductor layers, laterally paired second p-type silicon semiconductor layers, and laterally paired n-type silicon semiconductor layers, by an epitaxial growth method. On the second n-type silicon semiconductor layer on the right side, there are successively formed a third p-type silicon semiconductor layer, a third n-type silicon semiconductor layer and a fourth p-type silicon semiconductor layer. The left first n-type silicon semiconductor layer, left second p-type silicon semiconductor layer and left second n-type silicon semiconductor layer form a first insular multilayered portion forming an n-channel MOSFET. The third p-type silicon semiconductor layer, third n-type silicon semiconductor layer and fourth p-type silicon semiconductor layer form a second insular portion forming a p-channel MOSFET.

Abstract: Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment. P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

Abstract: On a semiconductor substrate made of p-type silicon, there are formed, in a successively layered fashion, a first p-type silicon semiconductor layer, laterally paired first n-type silicon semiconductor layers, laterally paired second p-type silicon semiconductor layers, and laterally paired n-type silicon semiconductor layers, by an epitaxial growth method. On the second n-type silicon semiconductor layer on the right side, there are successively formed a third p-type silicon semiconductor layer, a third n-type silicon semiconductor layer and a fourth p-type silicon semiconductor layer. The left first n-type silicon semiconductor layer, left second p-type silicon semiconductor layer and left second n-type silicon semiconductor layer form a first insular multilayered portion forming an n-channel MOSFET. The third p-type silicon semiconductor layer, third n-type silicon semiconductor layer and fourth p-type silicon semiconductor layer form a second insular portion forming a p-channel MOSFET.

Abstract: Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

Abstract: Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

Abstract: The adhesion between a metallic silicide film and a dielectric layer of a semiconductor device is improved. Formed on a silicon substrate is a gate dielectric layer formed on which is a metallic silicide film. A silicon dielectric layer of a rich-in-silicon-content type, which have a silicon content higher than a silicon content according to the stoichiometric composition formula, is deposited on the metallic silicide film. Because of this arrangement, a semiconductor device which is free from film peeling and which has an electrode wire with a low electrical resistance is achievable without decreasing the concentration of impurity at an electrode. If a passivation silicon oxide layer whose composition is close to a composition according to the stoichiometric composition formula is formed on the silicon oxide layer of a rich-in-silicon-content type, the degradation of the inside of an electrode, and the degradation of a gate oxide layer both caused by unwanted impurities from the outside can be prevented.

Abstract: Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.