Patents by Inventor Hirokazu Ishida
Hirokazu Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110237191Abstract: A short range wireless communication apparatus is disclosed. When multiple communication protocols including a first communication protocol and a second communication protocol are simultaneously connected between the short range wireless communication apparatus and another short range wireless communication apparatus, the short range wireless communication apparatus notifies the another short range wireless communication apparatus a second communication protocol connection request if the first communication protocol is disconnected in response to transmission of a first communication protocol disconnection request to the another short range wireless communication apparatus and then the second communication protocol is disconnected in response to transmission of a second communication protocol disconnection request from the another short range wireless communication apparatus.Type: ApplicationFiled: July 5, 2010Publication date: September 29, 2011Applicants: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Soichi Saito, Suguru Matsushita, Takahisa Ozaki, Hirokazu Ishida, Shinichi Yamamoto, Kazushige Hayashi
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Patent number: 7986000Abstract: A semiconductor device is formed on a SOI substrate having a semiconductor substrate, a buried oxide film formed on the semiconductor substrate, and a semiconductor layer formed on the buried oxide film, the semiconductor substrate having a first conductive type, the semiconductor layer having a second conductive type, wherein the buried oxide film has a first opening opened therethrough for communicating the semiconductor substrate with the semiconductor layer, the semiconductor layer is arranged to have a first buried portion buried in the first opening in contact with the semiconductor substrate and a semiconductor layer main portion positioned on the first buried portion and on the buried oxide film, the semiconductor substrate has a connection layer buried in a surface of the semiconductor substrate and electrically connected to the first buried portion in the first opening, the connection layer having the second conductive type, and the semiconductor device includes a contact electrode buried in a seconType: GrantFiled: September 22, 2009Date of Patent: July 26, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Mizukami, Kiyohito Nishihara, Masaki Kondo, Takashi Izumida, Hirokazu Ishida, Atsushi Fukumoto, Fumiki Aiso, Daigo Ichinose, Tadashi Iguchi
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Patent number: 7938566Abstract: There is provided a cover panel including a lighting device which is attachable without a mounting seat. A cover panel 1 includes a panel main body 5 fixed on an instrument panel 3 in an interior of an automobile and a lighting device 6 provided inside the panel main body 5. The panel main body 5 comprises an opening 7 which forms a gap between itself and the instrument panel 3, and light emitted through the opening 7 from the lighting device 6 illuminates the interior of the automobile. The panel main body 5 and the lighting device 6 are integrated and are fixed on the instrument panel 3, so that the cover panel 1 including the lighting device 6 can be fixed on the instrument panel 3 without utilizing the mounting seat as was conventionally done.Type: GrantFiled: October 14, 2008Date of Patent: May 10, 2011Assignee: Honda Access CorporationInventors: Hirokazu Ishida, Tomoki Kawamura, Yoku Tahira
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Patent number: 7879658Abstract: A semiconductor device includes a silicon crystal layer on an insulating layer, the silicon crystal layer containing a crystal lattice mismatch plane, a memory cell array portion on the silicon crystal layer, the memory cell array portion including memory strings, each of the memory strings including nonvolatile memory cell transistors connected in series in a first direction, the memory strings being arranged in a second direction orthogonal to the first direction, the crystal lattice mismatch plane crossing the silicon crystal along the second direction without passing under gates of the nonvolatile memory cell transistors as viewed from a top of the silicon crystal layer, or crossing the silicon crystal along the first direction with passing under gates of the nonvolatile memory cell transistors as viewed from the top of the silicon crystal layer.Type: GrantFiled: February 29, 2008Date of Patent: February 1, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yoshio Ozawa, Ichiro Mizushima, Takashi Suzuki, Hirokazu Ishida, Yoshitaka Tsunashima
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Publication number: 20110018048Abstract: According to an aspect of the invention, there is provided a semiconductor device comprising a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, a first conductive layer formed as a floating gate on the first insulating layer, a second insulating layer formed as an interelectrode insulating film on the first conductive layer, and comprising three layers of a first film mainly including silicon and oxygen, a second film mainly including silicon and nitrogen, and a third film mainly including silicon and oxygen, wherein a silicon and nitrogen composition ratio of the second film is in a state in which the silicon is in excess of a stoichiometric composition, and a second conductive layer formed as a control gate on the second insulating film.Type: ApplicationFiled: October 1, 2010Publication date: January 27, 2011Inventors: Masayuki Tanaka, Hirokazu Ishida
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Patent number: 7863166Abstract: A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.Type: GrantFiled: December 23, 2009Date of Patent: January 4, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Suzuki, Hirokazu Ishida, Ichiro Mizushima, Yoshio Ozawa, Fumiki Aiso, Katsuyuki Sekine, Takashi Nakao, Yoshihiko Saito
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Publication number: 20100331044Abstract: An in-vehicle hands-free phone system includes: a base station; a portable terminal that is wirelessly connected to the base station; and an in-vehicle device that includes: an information acquisition portion that acquires information about a portable terminal that is connected to the in-vehicle device; a storage portion that stores a number sequence whose intermediate portion includes a predetermined code; and a tone sending-out control portion that sends the number sequence stored in the storage portion to the portable terminal and causes the portable terminal to send out the number sequence in a tone. The tone sending-out control portion determines a tone sending-out behavior about a number sequence part that is subsequent to the predetermined code on the basis of the information acquired by the information acquisition portion.Type: ApplicationFiled: June 24, 2010Publication date: December 30, 2010Applicants: Toyota Jidosha Kabushiki Kaisha, Denso CorporationInventors: Kazushige Hayashi, Soichi Saito, Suguru Matsushita, Takahisa Ozaki, Hirokazu Ishida
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Patent number: 7842564Abstract: In a method of manufacturing a semiconductor memory device, an opening is made in a part of an insulating film formed on a silicon substrate. An amorphous silicon thin film is formed on the insulating film in which the opening has been made and inside the opening. Then, a monocrystal is solid-phase-grown in the amorphous silicon thin film, with the opening as a seed, thereby forming a monocrystalline silicon layer. Then, the monocrystalline silicon layer is heat-treated in an oxidizing atmosphere, thereby thinning the monocrystalline silicon layer and reducing the defect density. Then, a memory cell array is formed on the monocrystalline silicon layer which has been thinned and whose defect density has been reduced.Type: GrantFiled: July 3, 2008Date of Patent: November 30, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Ichiro Mizushima, Hirokazu Ishida, Yoshio Ozawa, Takashi Suzuki, Fumiki Aiso, Makoto Mizukami
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Patent number: 7833856Abstract: According to an aspect of the invention, there is provided a semiconductor device comprising a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, a first conductive layer formed as a floating gate on the first insulating layer, a second insulating layer formed as an interelectrode insulating film on the first conductive layer, and comprising three layers of a first film mainly including silicon and oxygen, a second film mainly including silicon and nitrogen, and a third film mainly including silicon and oxygen, wherein a silicon and nitrogen composition ratio of the second film is in a state in which the silicon is in excess of a stoichiometric composition, and a second conductive layer formed as a control gate on the second insulating film.Type: GrantFiled: May 21, 2007Date of Patent: November 16, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Tanaka, Hirokazu Ishida
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Patent number: 7819155Abstract: The present invention provides a rubber composition for a tire that is capable of improving air permeability resistance while preventing chipping of the bead toe and a pneumatic tire comprising the rubber composition. Specifically, the present invention relates to a rubber composition for a tire containing a composite material comprising rubber, polyolefin and nylon; the composite material being contained so that the content of nylon is 1 to 40 parts by weight based on 100 parts by weight of the total rubber component in the rubber composition.Type: GrantFiled: March 9, 2005Date of Patent: October 26, 2010Assignee: Sumitomo Rubber Industries, Ltd.Inventor: Hirokazu Ishida
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Publication number: 20100255671Abstract: A nonvolatile semiconductor memory device includes a first dielectric layer formed on the major surface of a semiconductor substrate, a floating gate electrode layer formed on the first dielectric layer, a second dielectric layer obtained by sequentially forming, on the floating gate electrode layer, a lower dielectric film mainly containing silicon and nitrogen, an intermediate dielectric film, and an upper dielectric film mainly containing silicon and nitrogen, a control gate electrode layer formed on the second dielectric layer, and a buried dielectric layer formed by covering the two side surfaces in the gate width direction of the stacked structure including the above-mentioned layers. The nonvolatile semiconductor memory device further includes a silicon oxide film formed near the buried dielectric layer in the interface between the floating gate electrode layer and lower dielectric film.Type: ApplicationFiled: June 17, 2010Publication date: October 7, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Hirokazu Ishida, Masayuki Tanaka
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Patent number: 7772636Abstract: A nonvolatile semiconductor memory device includes a first dielectric layer formed on the major surface of a semiconductor substrate, a floating gate electrode layer formed on the first dielectric layer, a second dielectric layer obtained by sequentially forming, on the floating gate electrode layer, a lower dielectric film mainly containing silicon and nitrogen, an intermediate dielectric film, and an upper dielectric film mainly containing silicon and nitrogen, a control gate electrode layer formed on the second dielectric layer, and a buried dielectric layer formed by covering the two side surfaces in the gate width direction of the stacked structure including the above-mentioned layers. The nonvolatile semiconductor memory device further includes a silicon oxide film formed near the buried dielectric layer in the interface between the floating gate electrode layer and lower dielectric film.Type: GrantFiled: April 19, 2007Date of Patent: August 10, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hirokazu Ishida, Masayuki Tanaka
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Publication number: 20100163151Abstract: A cushioning rubber composition contains 5 to 20 parts by mass of first carbon black having an iodine adsorption number of 50 to 70 mg/g and a dibutyl phthalate oil absorption of 130 to 150 ml/100 g and 15 to 30 parts by mass of second carbon black having an iodine adsorption number of 110 to 130 mg/g and a dibutyl phthalate oil absorption of 105 to 120 ml/100 g as well as sulfur and a vulcanization accelerator with respect to 100 parts by mass of a rubber component, while the mass ratio of sulfur to the vulcanization accelerator is 1.0 to 2.3.Type: ApplicationFiled: December 14, 2009Publication date: July 1, 2010Inventor: Hirokazu Ishida
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Publication number: 20100168312Abstract: Abrasion resistance can be improved without impairing tip cut resistance by using polybutadiene comprising specific syndiotactic-1,2-polybutadiene in a tread rubber. Namely, the present invention provides a rubber composition for a tread which comprises a rubber component comprising 10 to 30% by weight of a butadiene rubber in which syndiotactic-1,2-polybutadiene having an average primary particle diameter of not more than 100 nm is dispersed in the butadiene rubber.Type: ApplicationFiled: December 25, 2006Publication date: July 1, 2010Inventors: Hirokazu Ishida, Masataka Hiro, Takashi Wada
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Publication number: 20100117135Abstract: A semiconductor device is formed on a SOI substrate having a semiconductor substrate, a buried oxide film formed on the semiconductor substrate, and a semiconductor layer formed on the buried oxide film, the semiconductor substrate having a first conductive type, the semiconductor layer having a second conductive type, wherein the buried oxide film has a first opening opened therethrough for communicating the semiconductor substrate with the semiconductor layer, the semiconductor layer is arranged to have a first buried portion buried in the first opening in contact with the semiconductor substrate and a semiconductor layer main portion positioned on the first buried portion and on the buried oxide film, the semiconductor substrate has a connection layer buried in a surface of the semiconductor substrate and electrically connected to the first buried portion in the first opening, the connection layer having the second conductive type, and the semiconductor device includes a contact electrode buried in a seconType: ApplicationFiled: September 22, 2009Publication date: May 13, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Makoto MIZUKAMI, Kiyohito Nishihara, Masaki Kondo, Takashi Izumida, Hirokazu Ishida, Atsushi Fukumoto, Fumiki Aiso, Daigo Ichinose, Tadashi Iguchi
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Patent number: 7714373Abstract: There is disclosed a semiconductor device including a plurality of memory cell transistors, each memory cell transistor including a floating gate electrode isolated from each other via an isolation insulating film every memory cell transistor, an inter-electrode insulating film comprising a HfxAl1-xOy film (0.8?x?0.95) formed on the floating gate electrode, and a control gate electrode formed on the inter-electrode insulating film, wherein the memory cell transistors are arrayed to form a memory cell array.Type: GrantFiled: July 5, 2007Date of Patent: May 11, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Katsuaki Natori, Masayuki Tanaka, Katsuyuki Sekine, Hirokazu Ishida, Masumi Matsuzaki, Yoshio Ozawa
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Publication number: 20100112791Abstract: A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.Type: ApplicationFiled: December 23, 2009Publication date: May 6, 2010Inventors: Takashi Suzuki, Hirokazu Ishida, Ichiro Mizushima, Yoshio Ozawa, Fumiki Aiso, Katsuyuki Sekine, Takashi Nakao, Yoshihiko Saito
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Publication number: 20100093916Abstract: A rubber composition for sidewall contains 10 to 40 mass % syndiotactic-1,2-polybutadiene-containing polybutadiene rubber and 10 to 30 mass % tin-modified polybutadiene rubber in a polymer component, and contains 10 to 40 parts by mass silica with respect to 100 parts by mass polymer component. Thus, cut resistance and ozone resistance as well as fuel efficiency of a car can be improved.Type: ApplicationFiled: September 17, 2009Publication date: April 15, 2010Inventor: Hirokazu ISHIDA
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Publication number: 20100048799Abstract: The object of the present invention is to provide a rubber composition having high breaking strength, excellent in bead durability without the generation of rubber cracking during mounting and demounting of the rim, and excellent in fuel efficiency. The present invention relates a rubber composition for a chafer comprising: (A) a diene rubber comprising (A1) 10 to 60% by mass of a butadiene rubber containing 2.5 to 20% by mass of a 1,2-syndiotactic polybutadiene crystal, (A2) 5 to 50% by mass of a tin-modified butadiene rubber polymerized with a lithium initiator and having 50 to 3000 ppm content of tin atoms, 5 to 50% by mass of vinyl bond amount and a molecular weight distribution of at most 2.0, and (A3) 20 to 75% by mass of a diene rubber other than the butadiene rubber (A1) and the tin-modified butadiene rubber (A2); and (B) 5 to 30 parts by mass of silica (B) based on 100 parts by mass of the diene rubber components, wherein elongation at break of the rubber composition for a chafer is at least 280%.Type: ApplicationFiled: July 10, 2009Publication date: February 25, 2010Inventors: Tatsuya Miyazaki, Hirokazu Ishida
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Patent number: 7651930Abstract: A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.Type: GrantFiled: June 26, 2008Date of Patent: January 26, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Suzuki, Hirokazu Ishida, Ichiro Mizushima, Yoshio Ozawa, Fumiki Aiso, Katsuyuki Sekine, Takashi Nakao, Yoshihiko Saito