Patents by Inventor Hirokazu Ishida

Hirokazu Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7629232
    Abstract: A non-volatile semiconductor storage device having a high-dielectric-constant insulator and a manufacturing method thereof suitable for miniaturization are disclosed. According to one aspect of the present invention, it is provided a semiconductor storage device comprising a semiconductor substrate, a plurality of first conductor layers formed on the semiconductor substrate through a first insulator, an isolation formed between the plurality of first conductor layers, a silicon oxide film formed on the first conductor layer, a high-dielectric-constant insulator formed on the silicon oxide film and the isolation and being diffused silicon and oxygen at least in a surface thereof contacting with the silicon oxide film, and a second conductor film formed above the high-dielectric-constant insulator.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: December 8, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Hirokazu Ishida
  • Patent number: 7612404
    Abstract: A semiconductor device includes semiconductor substrate, isolation insulating film, nonvolatile memory cells, each of the cells including tunnel insulating film, FG electrode, CG electrode, interelectrode insulating film between the CG and FG electrodes and including a first insulating film and a second insulating film on the first insulating film and having higher permittivity than the first insulating film, the interelectrode insulating film being provided on a side wall of the floating gate electrode in a cross-section view of a channel width direction of the cell, thickness of the interelectrode insulating film increasing from an upper portion of the side wall toward a lower portion of the side wall, thickness of the second insulating film on an upper corner of the FG electrode being thicker than thickness of the second insulating film on the other portions of the side wall in the cross-section view of the channel width direction.
    Type: Grant
    Filed: April 13, 2007
    Date of Patent: November 3, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihito Yamamoto, Masayuki Tanaka, Katsuyuki Sekine, Daisuke Nishida, Ryota Fujisuka, Katsuaki Natori, Hirokazu Ishida, Yoshio Ozawa
  • Publication number: 20090196058
    Abstract: There is provided a cover panel including a lighting device which is attachable without a mounting seat. A cover panel 1 includes a panel main body 5 fixed on an instrument panel 3 in an interior of an automobile and a lighting device 6 provided inside the panel main body 5. The panel main body 5 comprises an opening 7 which forms a gap between itself and the instrument panel 3, and light emitted through the opening 7 from the lighting device 6 illuminates the interior of the automobile. The panel main body 5 and the lighting device 6 are integrated and are fixed on the instrument panel 3, so that the cover panel 1 including the lighting device 6 can be fixed on the instrument panel 3 without utilizing the mounting seat as was conventionally done.
    Type: Application
    Filed: October 14, 2008
    Publication date: August 6, 2009
    Applicant: HONDA ACCESS CORP.
    Inventors: Hirokazu Ishida, Tomoki Kawamura, Yoku Tahira
  • Publication number: 20090121279
    Abstract: A semiconductor device includes a single crystal silicon substrate an insulating layer partially formed on the single crystal silicon substrate, a single crystal silicon layer formed on the single crystal silicon substrate and the insulating layer, and containing a defect layer resulting from an excessive group IV element, and a plurality of first gate structures for memory cells, each including a first gate insulating film formed on the single crystal silicon layer, a charge storage layer formed on the first gate insulating film, a second gate insulating film formed on the charge storage layer, and a control gate electrode formed on the second gate insulating film.
    Type: Application
    Filed: October 10, 2008
    Publication date: May 14, 2009
    Inventors: Hirokazu Ishida, Takashi Suzuki, Yoshio Ozawa, Ichiro Mizushima, Yoshitaka Tsunashima
  • Publication number: 20090014828
    Abstract: In a method of manufacturing a semiconductor memory device, an opening is made in a part of an insulating film formed on a silicon substrate. An amorphous silicon thin film is formed on the insulating film in which the opening has been made and inside the opening. Then, a monocrystal is solid-phase-grown in the amorphous silicon thin film, with the opening as a seed, thereby forming a monocrystalline silicon layer. Then, the monocrystalline silicon layer is heat-treated in an oxidizing atmosphere, thereby thinning the monocrystalline silicon layer and reducing the defect density. Then, a memory cell array is formed on the monocrystalline silicon layer which has been thinned and whose defect density has been reduced.
    Type: Application
    Filed: July 3, 2008
    Publication date: January 15, 2009
    Inventors: Ichiro MIZUSHIMA, Hirokazu Ishida, Yoshio Ozawa, Takashi Suzuki, Fumiki Aiso, Makoto Mizukami
  • Publication number: 20090005481
    Abstract: A rubber composition for a tire comprising a rubber component containing at least one of a natural rubber and an epoxidized natural rubber, not less than 15 parts by mass of silica based on 100 parts by mass of the rubber component, and not less than 0.5 part by mass of calcium stearate based on 100 parts by mass of the rubber component, a tire member made using the rubber composition for a tire, and a tire made using the tire member.
    Type: Application
    Filed: June 13, 2008
    Publication date: January 1, 2009
    Inventors: Hirokazu Ishida, Michio Hirayama
  • Publication number: 20090000720
    Abstract: A rubber composition for a sidewall, in which balance between tip cut resistance and heat build-up property of a sidewall is enhanced, is provided. Namely, the present invention relates to a rubber composition for a sidewall, comprising a rubber component comprising 10 to 60% by weight of a butadiene rubber, wherein syndiotactic-1,2-polybutadiene having an average primary particle diameter of not more than 100 nm is dispersed in the butadiene rubber.
    Type: Application
    Filed: December 25, 2006
    Publication date: January 1, 2009
    Inventors: Hirokazu Ishida, Hirotoshi Otsuki, Takashi Wada
  • Publication number: 20090004833
    Abstract: A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.
    Type: Application
    Filed: June 26, 2008
    Publication date: January 1, 2009
    Inventors: Takashi Suzuki, Hirokazu Ishida, Ichiro Mizushima, Yoshio Ozawa, Fumiki Aiso, Katsuyuki Sekine, Takashi Nakao, Yoshihiko Saito
  • Publication number: 20080311734
    Abstract: A non-volatile semiconductor storage device having a high-dielectric-constant insulator and a manufacturing method thereof suitable for miniaturization are disclosed. According to one aspect of the present invention, it is provided a semiconductor storage device comprising a semiconductor substrate, a plurality of first conductor layers formed on the semiconductor substrate through a first insulator, an isolation formed between the plurality of first conductor layers, a silicon oxide film formed on the first conductor layer, a high-dielectric-constant insulator formed on the silicon oxide film and the isolation and being diffused silicon and oxygen at least in a surface thereof contacting with the silicon oxide film, and a second conductor film formed above the high-dielectric-constant insulator.
    Type: Application
    Filed: August 18, 2008
    Publication date: December 18, 2008
    Inventors: Masayuki TANAKA, Hirokazu Ishida
  • Publication number: 20080211004
    Abstract: A semiconductor device includes a silicon crystal layer on an insulating layer, the silicon crystal layer containing a crystal lattice mismatch plane, a memory cell array portion on the silicon crystal layer, the memory cell array portion including memory strings, each of the memory strings including nonvolatile memory cell transistors connected in series in a first direction, the memory strings being arranged in a second direction orthogonal to the first direction, the crystal lattice mismatch plane crossing the silicon crystal along the second direction without passing under gates of the nonvolatile memory cell transistors as viewed from a top of the silicon crystal layer, or crossing the silicon crystal along the first direction with passing under gates of the nonvolatile memory cell transistors as viewed from the top of the silicon crystal layer.
    Type: Application
    Filed: February 29, 2008
    Publication date: September 4, 2008
    Inventors: Yoshio OZAWA, Ichiro Mizushima, Takashi Suzuki, Hirokazu Ishida, Yoshitaka Tsunashima
  • Publication number: 20080179655
    Abstract: A nonvolatile semiconductor memory device includes a first insulator, first conductor, element isolation insulator, second insulator and second conductor. The first insulator is formed on the main surface of a substrate and the first conductor is formed on the first insulator. The element isolation insulator is filled into at least part of both side surfaces of the first insulator in a gate width direction thereof and both side surfaces of the first conductor in a gate width direction thereof and is so formed that the upper surface thereof will be set with height between those of the upper and bottom surfaces of the first conductor. The second insulator includes a three-layered insulating film formed of a silicon oxide film, a silicon oxynitride film and a silicon oxide film formed on the first conductor and element isolation insulator. The second conductor is formed on the second insulator.
    Type: Application
    Filed: January 25, 2008
    Publication date: July 31, 2008
    Inventors: Hirokazu Ishida, Masayuki Tanaka, Yoshio Ozawa
  • Publication number: 20080176389
    Abstract: A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate of polysilicon provided on each of the element formation regions through a first insulation film, a second insulation film, provided on the floating gate, containing a metal element, a control gate of polysilicon, provided on the second insulation film, and source/drain regions provided in the semiconductor substrate, both a polysilicon conductive layer containing a metal element and a mutual diffusion layer composed of a silicate layer of a mixed oxide material composed of a silicon element contained in the floating gate and the control gate and a metal element contained in the second insulation film are provided on a surface of each of the floating gate and the control gate, respectively.
    Type: Application
    Filed: March 24, 2008
    Publication date: July 24, 2008
    Inventors: Masayuki Tanaka, Yoshio Ozawa, Hirokazu Ishida, Katsuaki Natori, Seiji Inumiya
  • Patent number: 7368780
    Abstract: A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate of polysilicon provided on each of the element formation regions through a first insulation film, a second insulation film, provided on the floating gate, containing a metal element, a control gate of polysilicon, provided on the second insulation film, and source/drain regions provided in the semiconductor substrate, both a polysilicon conductive layer containing a metal element and a mutual diffusion layer composed of a silicate layer of a mixed oxide material composed of a silicon element contained in the floating gate and the control gate and a metal element contained in the second insulation film are provided on a surface of each of the floating gate and the control gate, respectively.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: May 6, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Yoshio Ozawa, Hirokazu Ishida, Katsuaki Natori, Seiji Inumiya
  • Publication number: 20080017914
    Abstract: There is disclosed a semiconductor device including a plurality of memory cell transistors, each memory cell transistor including a floating gate electrode isolated from each other via an isolation insulating film every memory cell transistor, an inter-electrode insulating film comprising a HfxAl1-xOy film (0.8?x?0.95) formed on the floating gate electrode, and a control gate electrode formed on the inter-electrode insulating film, wherein the memory cell transistors are arrayed to form a memory cell array.
    Type: Application
    Filed: July 5, 2007
    Publication date: January 24, 2008
    Inventors: Katsuaki Natori, Masayuki Tanaka, Katsuyuki Sekine, Hirokazu Ishida, Masumi Matsuzaki, Yoshio Ozawa
  • Publication number: 20070267682
    Abstract: According to an aspect of the invention, there is provided a semiconductor device comprising a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, a first conductive layer formed as a floating gate on the first insulating layer, a second insulating layer formed as an interelectrode insulating film on the first conductive layer, and comprising three layers of a first film mainly including silicon and oxygen, a second film mainly including silicon and nitrogen, and a third film mainly including silicon and oxygen, wherein a silicon and nitrogen composition ratio of the second film is in a state in which the silicon is in excess of a stoichiometric composition, and a second conductive layer formed as a control gate on the second insulating film.
    Type: Application
    Filed: May 21, 2007
    Publication date: November 22, 2007
    Inventors: Masayuki Tanaka, Hirokazu Ishida
  • Patent number: 7294878
    Abstract: A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate provided on each of the element formation regions through a first gate insulation film, a control gate provided on the floating gate through a second gate insulation film, and source/drain regions provided in the semiconductor substrate, wherein a mutual diffusion layer is provided at least at an interface between the second gate insulation film and the control gate.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: November 13, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Yoshio Ozawa, Hirokazu Ishida, Katsuaki Natori, Seiji Inumiya
  • Publication number: 20070249120
    Abstract: A nonvolatile semiconductor memory device includes a first dielectric layer formed on the major surface of a semiconductor substrate, a floating gate electrode layer formed on the first dielectric layer, a second dielectric layer obtained by sequentially forming, on the floating gate electrode layer, a lower dielectric film mainly containing silicon and nitrogen, an intermediate dielectric film, and an upper dielectric film mainly containing silicon and nitrogen, a control gate electrode layer formed on the second dielectric layer, and a buried dielectric layer formed by covering the two side surfaces in the gate width direction of the stacked structure including the above-mentioned layers. The nonvolatile semiconductor memory device further includes a silicon oxide film formed near the buried dielectric layer in the interface between the floating gate electrode layer and lower dielectric film.
    Type: Application
    Filed: April 19, 2007
    Publication date: October 25, 2007
    Inventors: Hirokazu Ishida, Masayuki Tanaka
  • Publication number: 20070241388
    Abstract: A semiconductor device includes semiconductor substrate, isolation insulating film, nonvolatile memory cells, each of the cells including tunnel insulating film, FG electrode, CG electrode, interelectrode insulating film between the CG and FG electrodes and including a first insulating film and a second insulating film on the first insulating film and having higher permittivity than the first insulating film, the interelectrode insulating film being provided on a side wall of the floating gate electrode in a cross-section view of a channel width direction of the cell, thickness of the interelectrode insulating film increasing from an upper portion of the side wall toward a lower portion of the side wall, thickness of the second insulating film on an upper corner of the FG electrode being thicker than thickness of the second insulating film on the other portions of the side wall in the cross-section view of the channel width direction.
    Type: Application
    Filed: April 13, 2007
    Publication date: October 18, 2007
    Inventors: Akihito Yamamoto, Masayuki Tanaka, Katsuyuki Sekine, Daisuke Nishida, Ryota Fujitsuka, Katsuaki Natori, Hirokazu Ishida, Yoshio Ozawa
  • Publication number: 20070235799
    Abstract: A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate of polysilicon provided on each of the element formation regions through a first insulation film, a second insulation film, provided on the floating gate, containing a metal element, a control gate of polysilicon, provided on the second insulation film, and source/drain regions provided in the semiconductor substrate, both a polysilicon conductive layer containing a metal element and a mutual diffusion layer composed of a silicate layer of a mixed oxide material composed of a silicon element contained in the floating gate and the control gate and a metal element contained in the second insulation film are provided on a surface of each of the floating gate and the control gate, respectively.
    Type: Application
    Filed: June 14, 2007
    Publication date: October 11, 2007
    Inventors: Masayuki Tanaka, Yoshio Ozawa, Hirokazu Ishida, Katsuaki Natori, Seiji Inumiya
  • Publication number: 20070075357
    Abstract: A non-volatile semiconductor storage device having a high-dielectric-constant insulator and a manufacturing method thereof suitable for miniaturization are disclosed. According to one aspect of the present invention, it is provided a semiconductor storage device comprising a semiconductor substrate, a plurality of first conductor layers formed on the semiconductor substrate through a first insulator, an isolation formed between the plurality of first conductor layers, a silicon oxide film formed on the first conductor layer, a high-dielectric-constant insulator formed on the silicon oxide film and the isolation and being diffused silicon and oxygen at least in a surface thereof contacting with the silicon oxide film, and a second conductor film formed above the high-dielectric-constant insulator.
    Type: Application
    Filed: February 1, 2006
    Publication date: April 5, 2007
    Inventors: Masayuki Tanaka, Hirokazu Ishida