Abstract: A flow controller and a flow controlling method are adapted to be released from conventional restrictions by using a novel type called a pulse shot type. A pulse shot (opening/closing operation of a first cutoff valve (12) and, after that, opening/closing operation of a second cutoff valve (17)) is repeated. Simultaneously, a volume flow Q of process gas exhausted from the second cutoff valve (17) per unit time on the basis of after-filling pressure and after-exhaust pressure of the process gas in a gas filling capacity (13) measure by a pressure sensor (14). Furthermore, a mode of the pulse shot is changed to control the volume flow Q of the process gas exhausted from the second cutoff valve (17) per unit time.

Abstract: A power-on reset circuit comprises a power supply voltage detection circuit that detects a rise of a power supply voltage and that changes a logic level of a first internal node; a capacitor charge/discharge circuit that charges and discharges a capacitor according to the first internal node level and that in an event that the power supply voltage is reduced, discharges the capacitor to follow the event; and a reset pulse generation circuit that before the power supply voltage rises higher than the predetermined voltage, outputs a first output voltage to an output node and that after the power supply voltage has risen higher than the predetermined voltage, outputs a second output voltage to the output node upon detecting that a charge level of the capacitor has become higher than a charge level detection voltage.

Abstract: In a negative voltage output charge pump circuit, first a capacitor C1 is charged with a positive voltage Vin relative to a reference voltage, and then the high-potential terminal A of the capacitor C1 is made to conduct to the reference voltage and simultaneously the low-potential terminal B of the capacitor C1 is made to conduct to an output terminal OUT so that the voltage with which the capacitor C1 is charged is output as a negative voltage −Vin. Here, at least one of the switching device DP1 that is kept on while the capacitor C1 is being charged so as to apply the reference voltage to the point B and the switching device DP2 that is kept on while the negative voltage is being output so as to make the point B conduct to the output terminal OUT is a depletion-type transistor. This configuration makes it possible to realize a negative voltage output charge pump circuit that is free from malfunctioning caused by a parasitic device, that operates with low loss, and that can be produced at low costs.

Abstract: A Hall device biasing circuit includes a plurality of terminals for applying a bias voltage to a plurality of Hall devices connected in series, respectively. A magnetism detection circuit includes a plurality of Hall devices connected in series; and a Hall device biasing circuit including at least a plurality of terminals corresponding to the plurality of Hall devices for supplying a constant bias voltage to each of the plurality of Hall devices respectively from the plurality of terminals.

Abstract: In a negative voltage output charge pump circuit, first a capacitor C1 is charged with a positive voltage Vin relative to a reference voltage, and then the high-potential terminal A of the capacitor C1 is made to conduct to the reference voltage and simultaneously the low-potential terminal B of the capacitor C1 is made to conduct to an output terminal OUT so that the voltage with which the capacitor C1 is charged is output as a negative voltage −Vin. Here, at least one of the switching device DP1 that is kept on while the capacitor C1 is being charged so as to apply the reference voltage to the point B and the switching device DP2 that is kept on while the negative voltage is being output so as to make the point B conduct to the output terminal OUT is a depletion-type transistor. This configuration makes it possible to realize a negative voltage output charge pump circuit that is free from malfunctioning caused by a parasitic device, that operates with low loss, and that can be produced at low costs.

Abstract: A delay circuit in accordance with the present invention includes: a first I2L inverter and a second I2L inverter connected in cascade with each other; and a capacitor interposed between a ground and a connecting point of the first and second inverters, wherein: the delay circuit further includes a current adjusting circuit having at least one third I2L inverter with a plurality of output terminals at least one of which is connected to an input terminal of the third I2L inverter; and the current adjusting circuit is connected to adjust a charge current of the capacitor. The configuration provides a delay circuit of simple circuit structure that accounts for a small area in an integrated circuit and that is capable of introducing any given delay and also provides a ring oscillator incorporating the delay circuit.

Abstract: An IIL reset circuit includes an IIL inverter having input and output terminals, and a capacitor connected to the IIL inverter through the input terminal. When the IIL inverter is supplied with a constant current, it charges the capacitor through the input terminal, and outputs a reset pulse through the output terminal. The reset pulse has a pulse width that is determined based on both a current supplied to the capacitor, and on a capacitance of the capacitor.

Abstract: A delay circuit in accordance with the present invention includes: a first I2L inverter and a second I2L inverter connected in cascade with each other; and a capacitor interposed between a ground and a connecting point of the first and second inverters, wherein: the delay circuit further includes a current adjusting circuit having at least one third I2L inverter with a plurality of output terminals at least one of which is connected to an input terminal of the third I2L inverter; and the current adjusting circuit is connected to adjust a charge current of the capacitor. The configuration provides a delay circuit of simple circuit structure that accounts for a small area in an integrated circuit and that is capable of introducing any given delay and also provides a ring oscillator incorporating the delay circuit.