Patents by Inventor Hiromitsu Ishii

Hiromitsu Ishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040174483
    Abstract: A display device includes a substrate, a plurality of scanning lines formed in parallel with each other on the substrate in one direction, a plurality of data lines formed in parallel with each other on the substrate in orthogonal to the scanning lines, a thin film transistor being formed in the vicinity of each intersection of the scanning lines and the data lines and having a semiconductor thin film, a gate electrode connected to one of the scanning lines, a source electrode, a drain electrode connected to one of the scanning lines; pixel electrodes each connected to the source electrode of the thin film transistor, auxiliary capacitive electrodes each having an overlap region that overlaps with the pixel electrodes and forming an auxiliary capacitance with the pixel electrodes, a first insulating film arranged between the auxiliary capacitive electrodes and the data lines, and a second insulting film arranged between the pixel electrodes and the auxiliary capacitive electrodes.
    Type: Application
    Filed: March 4, 2004
    Publication date: September 9, 2004
    Inventors: Yayoi Nakamura, Hiromitsu Ishii, Shinichi Shimomaki, Hitoshi Watanabe
  • Patent number: 6678017
    Abstract: An active matrix display panel includes a plurality of pixel electrodes formed in a matrix manner, a plurality of switching elements connected with these pixel electrodes, a plurality of scan lines for supplying a scan signal to thin film transistors, and a plurality of data lines for supplying a display data signal. Components except for the pixel electrodes are covered with an overcoat film. Since a contact hole extending through this overcoat film and a contact hole extending through the overcoat film and a gate insulating film are simultaneously formed, a jumper line for connecting a disconnected portion of a protect ring, a surface layer of a data line connecting pad, and a line protecting film are formed at the same time as the pixel electrodes are formed. This reduces the number of fabrication steps. Components such as the data line and source and drain electrodes are formed by a three-layered structure of Cr(Chromium)/Al(Aluminum)/Cr(Chromium).
    Type: Grant
    Filed: June 4, 1999
    Date of Patent: January 13, 2004
    Assignee: Casio Computer Co., Ltd.
    Inventors: Shinichi Shimomaki, Makoto Miyagawa, Hiromitsu Ishii, Yayoi Nakamura
  • Patent number: 6653216
    Abstract: An active matrix substrate includes a line layer formed of an Al-based metal layer and a part of which is exposed through a contact hole formed in an insulating film. In the active matrix substrate, pixel electrodes are formed of an ITO film on the insulating film, and a jumper line for connecting a disconnected portion of a protect ring, a surface layer of a data line connecting pad, and a line protecting film are formed at the same time as the pixel electrodes are formed. This reduces the number of fabrication steps. The ITO film is patterned by dry etching due to reactive ion etching using a mixed gas of a hydrogen halide gas and an inert gas, with the temperatures of the center portion and peripheral portion of the substrate substantially equalized to each other.
    Type: Grant
    Filed: April 23, 2001
    Date of Patent: November 25, 2003
    Assignee: Casio Computer Co., Ltd.
    Inventors: Shinichi Shimomaki, Makoto Miyagawa, Hiromitsu Ishii, Yayoi Nakamura, Toshiaki Higashi
  • Publication number: 20030142255
    Abstract: There is provided a liquid crystal display apparatus including a first substrate, a second substrate having an inner surface opposing the first substrate. A liquid crystal is placed between the first and second substrates. A plurality of light-transmitting pixel electrodes are arranged between the inner surface of the second substrate and the liquid crystal. A reflecting layer is placed between each pixel electrode and the inner surface of the second substrate and has an area smaller than that of the pixel electrode.
    Type: Application
    Filed: January 29, 2003
    Publication date: July 31, 2003
    Applicant: Casio Computer Co., Ltd.
    Inventors: Hiromitsu Ishii, Shintaro Kuwayama
  • Patent number: 6377322
    Abstract: Each pair of gate lines GL are arranged aside a corresponding one of rows of pixel electrodes arranged in a matrix form, so as to sandwich pixel electrodes in the direction of columns, whereas each pair of TFTs are arranged to a sandwich corresponding one of the pixel electrodes, and each of data lines DL is arranged aside a corresponding one of columns of pixel electrodes. TFTs are connected to the pixel electrodes and to the gate lines GL so that the pixel electrodes of one row are selected when two of the gate lines GL sandwiching the pixel electrodes are selected. An end of a current path of each TFT is connected to the data line DL. When a pair of TFTs sandwiching one pixel electrode are simultaneously turned on, large current is supplied to the pixel electrode through the data line DL. Source electrode of TFT and source electrode of its proximate (adjacent) thin film transistor are formed by pattering the same metal layer, and share one current path connected to the data line DL.
    Type: Grant
    Filed: December 22, 1998
    Date of Patent: April 23, 2002
    Assignee: Casio Computer Co., Ltd.
    Inventors: Ikuhiro Yamaguchi, Hiromitsu Ishii
  • Publication number: 20010046001
    Abstract: Each pair of gate lines GL are arranged aside a corresponding one of rows of pixel electrodes arranged in a matrix form, so as to sandwich pixel electrodes in the direction of columns, whereas each pair of TFTs are arranged to a sandwich corresponding one of the pixel electrodes, and each of data lines DL is arranged aside a corresponding one of columns of pixel electrodes. TFTs are connected to the pixel electrodes and to the gate lines GL so that the pixel electrodes of one row are selected when two of the gate lines GL sandwiching the pixel electrodes are selected. An end of a current path of each TFT is connected to the data line DL. When a pair of TFTs sandwiching one pixel electrode are simultaneously turned on, large current is supplied to the pixel electrode through the data line DL. Source electrode of TFT and source electrode of its proximate (adjacent) thin film transistor are formed by pattering the same metal layer, and share one current path connected to the data line DL.
    Type: Application
    Filed: December 22, 1998
    Publication date: November 29, 2001
    Inventors: IKUHIRO YAMAGUCHI, HIROMITSU ISHII
  • Patent number: 6310683
    Abstract: A light beam emitted by a surface illuminant reaches the surface of a transparent base layer of a recess/projection detection optical element. A light beam emitted almost vertically is emitted to an air layer. A light beam incident on the transparent base layer at an angle larger than a total reflection angle returns to a two-dimensional photosensor at a portion contacting the air layer, but scatters in a transparent particle at a portion contacting the transparent particle. When a finger is brought into contact with a scattering reflection layer, the scattering reflection state does not change in an area corresponding to a valley of a fingertip. As indicated by an arrow, an amount of reflected light beam is large. In an area corresponding to a ridge of the fingertip, the light beam scattered by the transparent particle is absorbed. The amount of reflected light beam is small, as indicated by an arrow.
    Type: Grant
    Filed: August 3, 1998
    Date of Patent: October 30, 2001
    Assignee: Casio Computer Co., Ltd.
    Inventors: Minoru Fujiwara, Makoto Sasaki, Hiromitsu Ishii, Tetsuo Muto
  • Patent number: 6069019
    Abstract: According to the present invention, a gate insulation film, a silicon film and silicon nitride film are laminated on a gate backing pad made of a gate metal film, and etching is carried out on the silicon nitride film such that it remains on the gate backing pad as a protective insulation film. Thus, the corrosion of the gate backing pad, which is caused as the etching solution penetrate the silicon film in defect, can be prevented. Further, a protective semiconductor layer formed by patterning the protective insulation film and the silicon film, is formed above the gate backing pad. Thus, the gate backing pad can be protected from the etching solution during the patterning of the pixel electrode made of ITO. Therefore, the disconnection of the gate backing pad can be prevented.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: May 30, 2000
    Assignee: Casio Computer Co., Ltd.
    Inventors: Hiromitsu Ishii, Hisao Tosaka
  • Patent number: 5757028
    Abstract: A thin film transistor which can reduce production of leakage current between the source and drain electrodes and a fabricating method therefor, are disclosed. In the thin film transistor, an insulating film is formed on at least a portion of each side, corresponding to the region between the source and drain electrodes, of the peripheral side surface of the intrinsic semiconductor film, so that no metal silicide is formed thereon.
    Type: Grant
    Filed: September 25, 1997
    Date of Patent: May 26, 1998
    Assignee: Casio Computer Co., Ltd.
    Inventors: Kazuhiro Sasaki, Hiromitsu Ishii, Makoto Sasaki, Yoshitomo Wada
  • Patent number: 5755229
    Abstract: A pulse wave analysis device for analyzing the condition of a human body is disclosed. A cuff band is wrapped around the tip of the second finger of a subject's hand. When the operator depresses the beginning-of-measurement key, the finger tip is pressed at various pressures by means of an air pump and a pressure sensor. Pulse wave signals at different pressure values are automatically measured by an optical fingertip plethysmogram sensor. The signals are transmitted to a CPU through a BPF, an amplifier, and an ADC. The CPU performs FFT analyses on the signals and determines to which pattern from among the patterns stored in a ROM the pattern level of the pulse wave spectrum for a given pressure value is closest, and displays the result on a display unit as a test result indicating the viscoelasticity of the subject's peripheral circulation tissue.
    Type: Grant
    Filed: December 27, 1996
    Date of Patent: May 26, 1998
    Assignee: Seiko Epson Corporation
    Inventors: Kazuhiko Amano, Hiromitsu Ishii, Kazuo Kodama
  • Patent number: 5670938
    Abstract: In a fire alarm device for detecting the physical quantities of substances arising from the outbreak of a fire and giving a fire alarm, membership functions showing the correlation between an arising quantities calculated by the detected physical quantities and the danger degree which a man would feel with respect to the physical quantities are preset, the danger degree with respect to the arising value calculated by the physical quantities actually detected by a detection means is obtained by using the membership functions, and an alarm and control in accordance with the danger degree is given. Therefore, there is provided a fire alarm device capable of judging the outbreak of a fire based on an actual fire situation and giving an alarm and control in accordance with the degree of danger which a man would feel with respect to the scale, situation and so on of the fire.
    Type: Grant
    Filed: May 16, 1995
    Date of Patent: September 23, 1997
    Assignee: Hochiki Kabushiki Kaisha
    Inventors: Shigeru Ohtani, Hiromitsu Ishii, Takashi Ono
  • Patent number: 5623933
    Abstract: A pulse wave analysis device for analyzing the condition of a human body is disclosed. A cuff band is wrapped around the tip of the second finger of a subject's hand. When the operator depresses the beginning-of-measurement key, the finger tip is pressed at various pressures by means of an air pump and a pressure sensor. Pulse wave signals at different pressure values are automatically measured by an optical fingertip plethysmogram sensor. The signals are transmitted to a CPU through a BPF, an amplifier, and an ADC. The CPU performs FFT analyses on the signals and determines to which pattern from among the patterns stored in a ROM the pattern level of the pulse wave spectrum for a given pressure value is closest, and displays the result on a display unit as a test result indicating the viscoelasticity of the subject's peripheral circulation tissue.
    Type: Grant
    Filed: August 3, 1994
    Date of Patent: April 29, 1997
    Assignee: Seiko Epson Corporation
    Inventors: Kazuhiko Amano, Hiromitsu Ishii, Kazuo Kodama
  • Patent number: 5436614
    Abstract: A thermal analog fire detector which is excellent in measurement precision and resolution in both the high and low temperature ranges and which has a wide range of measuring temperatures. A constant voltage E from a constant voltage circuit is supplied to a CPU, an A/D converter and a constant current circuit. The constant current circuit is connected in series to a thermistor. The constant current circuit is constructed to supply a constant current, the value of which being variable in a plurality of stages, to the thermistor controlled by the CPU. The CPU switches the constant current of the constant current circuit according to the measured temperature data. A voltage V across the thermistor is converted into digital data by the A/D converter, and then the converted data is supplied to the CPU.
    Type: Grant
    Filed: July 2, 1993
    Date of Patent: July 25, 1995
    Assignee: Hochiki Kabushiki Kaisha
    Inventors: Yasuo Torikoshi, Hiromitsu Ishii
  • Patent number: 5427962
    Abstract: A method of manufacturing a thin-film transistor which comprises the steps of forming a gate electrode on an insulating substrate, a gate insulating film covering the gate electrode, and an i-type a-Si layer on the gate insulating film, forming a blocking film made of metal such as Cr or the like on a channel-forming region of the i-type a-Si layer, and forming an n-type a-Si layer covering the i-type a-Si layer and the blocking film, forming a metal layer on the n-type a-Si layer, and etching a predetermined portion of the n-type a-Si layer and a predetermined portion of the metal layer, thereby forming a source electrode and a drain electrode. That portion of the blocking film which is located below a gap between the source electrode and the drain electrode is removed from the i-type a-Si layer.
    Type: Grant
    Filed: November 10, 1992
    Date of Patent: June 27, 1995
    Assignee: Casio Computer Co., Ltd.
    Inventors: Makoto Sasaki, Hiromitsu Ishii, Kazuhiro Sasaki
  • Patent number: 5367179
    Abstract: A thin-film transistor comprises a gate electrode formed on an insulating substrate, a gate insulating film covering the gate electrode and the insulating substrate, an i-type semiconductor layer formed on the gate insulating film, and a source electrode and a drain electrode electrically connected to two ends of the i-type semiconductor layer, respectively. The gate electrode is made of aluminum alloy containing high-melting-point metal such as Ti and Ta and oxygen or nitrogen or both.
    Type: Grant
    Filed: November 12, 1992
    Date of Patent: November 22, 1994
    Assignee: Casio Computer Co., Ltd.
    Inventors: Hisatoshi Mori, Syunichi Sato, Naohiro Konya, Ichiro Ohno, Hiromitsu Ishii, Kunihiro Matsuda, Junji Shiota
  • Patent number: 5352907
    Abstract: A thin-film transistor includes a gate electrode and a semiconductor film consisting of amorphous silicon, formed on an insulating substrate to oppose each other through a gate insulating film, ohmic contact layers composed of n-type amorphous silicon doped with an impurity, electrically insulated from each other on the semiconductor film, and electrically connected to the semiconductor film, and source and drain electrodes arranged on the semiconductor film with a predetermined gap to form a channel portion, and electrically connected to the semiconductor film through the ohmic contact layers. The gate electrode and a portion surrounding the gate electrode are entirely formed into a continuous metal oxide film by a chemical reaction.
    Type: Grant
    Filed: March 24, 1992
    Date of Patent: October 4, 1994
    Assignee: Casio Computer Co., Ltd.
    Inventors: Kunihiro Matsuda, Hiromitsu Ishii, Naohiro Konya
  • Patent number: 5310823
    Abstract: A polyacetal resin composition having a volume resistivity lower than 10.sup.14 [.OMEGA..multidot.cm], which comprises (A) 100 parts by weight of a polyacetal resin and (B) 1 to 100 parts by weight of a polyether ester block copolymer which is derived from (a) a dicarboxylic acid component composed mainly of terephthalic acid, (b) a glycol component composed mainly of 1,4-butanediol and (c) a poly(ethylene oxide)glycol having a number average molecular weight of 500 to 20,000 and has a poly(ethylene oxide) dicarboxylate unit content of 20 to 95% by weight, has excellent antistatic characteristics and mechanical characteristics, and especially a high impact resistance.
    Type: Grant
    Filed: February 24, 1993
    Date of Patent: May 10, 1994
    Assignee: Toray Industries, Inc.
    Inventors: Masaki Kunitomi, Hiromitsu Ishii, Yoshiyuki Yamamoto
  • Patent number: 5289275
    Abstract: By using the ratio of the G component to the R component G/R, or the ratio of the B component to the R component B/R, from a television monitor image, and referring to a conversion table for converting to distribution temperature, a surface temperature of a flame is found for each pixel. An area in which luminance signals included in an image of a surveillance area exceed a prescribed level is sampled as a flame outline, and at least the distribution temperature of a sampled flame region is detected, and distance to a radiant energy source is measured. The amount of radiant energy from the radiant energy source is estimated by computation, based on the sampled flame area and its distribution temperature and the distance to the source of radiant energy.
    Type: Grant
    Filed: July 10, 1992
    Date of Patent: February 22, 1994
    Assignees: Hochiki Kabushiki Kaisha, Hiromitsu Ishii
    Inventors: Hiromitsu Ishii, Takashi Ono, Kiyoshi Watanabe
  • Patent number: 5243202
    Abstract: A thin-film transistor comprises a gate electrode formed on a glass substrate, a gate insulating film formed essentially over an entire surface of the substrate to cover the gate electrode, a non-single-crystal silicon semiconductor film placed on the gate insulating film to cover the gate electrode; and a drain electrode and a source electrode spaced a specified distance apart on the semiconductor film and electrically connected to the semiconductor film so as to form the channel region of the transistor. The gate electrode is made of titanium-containing aluminum.
    Type: Grant
    Filed: January 12, 1993
    Date of Patent: September 7, 1993
    Assignee: Casio Computer Co., Ltd.
    Inventors: Hisatoshi Mori, Syunichi Sato, Naohiro Konya, Ichiro Ohno, Hiromitsu Ishii, Kunihiro Matsuda
  • Patent number: 5225497
    Abstract: An elastic polyester is continuously prepared by continuously supplying an aromatic polyester and a lactone compound into an extruder which has (A) a cylinder having a shape of 3.ltoreq.L/D.ltoreq.70 (where L represents the length of the cylinder and D represents the inner diameter of the cylinder) and (B) at least one screw and wherein (C) the occupancy ratio of the space in the inner volume of the cylinder in the screw-attached state is not larger than 70%, and reacting the aromatic polyester with the lactone compound while performing melting, delivery and kneading in the extruder, according to this process, the reaction time can be shortened, and an elastic polyester can be easily prepared at a high efficiency by simplified apparatus and operations. The obtained elastic polyester has an excellent durability represented by heat resistance and weatherability and has an excellent rubbery elasticity and mechanical properties.
    Type: Grant
    Filed: January 17, 1991
    Date of Patent: July 6, 1993
    Assignee: Toray Industries, Inc.
    Inventors: Hiromitsu Ishii, Shoji Yamamoto, Yoshiyuki Yamamoto