Patents by Inventor Hironobu Shibata

Hironobu Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11956870
    Abstract: A light source device that supplies a constant current to a diode load that includes a plurality of light-emitting elements connected in series. The light source device includes a power supply circuit connected to the diode load and a peak current limiting circuit connected in series to the diode load. The peak current limiting circuit includes a current detector that is connected in series to the diode load and a current-regulating circuit that controls a current to the diode load by a detection voltage of the current detector. Further, the current detector has a series circuit including a resistor and a coil.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: April 9, 2024
    Assignee: NICHIA CORPORATION
    Inventors: Daisuke Mori, Hironobu Shibata, Ryosuke Mori, Masaki Omori, Hideki Kondo
  • Publication number: 20230023001
    Abstract: A light source device that supplies a constant current to a diode load that includes a plurality of light-emitting elements connected in series. The light source device includes a power supply circuit connected to the diode load and a peak current limiting circuit connected in series to the diode load. The peak current limiting circuit includes a current detector that is connected in series to the diode load and a current-regulating circuit that controls a current to the diode load by a detection voltage of the current detector. Further, the current detector has a series circuit including a resistor and a coil.
    Type: Application
    Filed: December 8, 2020
    Publication date: January 26, 2023
    Applicant: NICHIA CORPORATION
    Inventors: Daisuke MORI, Hironobu SHIBATA, Ryosuke MORI, Masaki OMORI, Hideki KONDO
  • Patent number: 11062832
    Abstract: A cavity is formed in a surface of a dielectric component on the permanent magnet side. The cavity has a bottom surface extending in a direction along one main surface and a side surface extending in a thickness direction crossing the bottom surface. At least a part of the permanent magnet is disposed in the cavity. A surface of at least a part of the permanent magnet disposed in the cavity is fixed to both of the bottom surface and the side surface through an adhesive.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: July 13, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tetsuya Ueda, Hironobu Shibata, Yukinobu Tarui, Hidenori Ishibashi
  • Publication number: 20210142935
    Abstract: A cavity is formed in a surface of a dielectric component on the permanent magnet side. The cavity has a bottom surface extending in a direction along one main surface and a side surface extending in a thickness direction crossing the bottom surface. At least a part of the permanent magnet is disposed in the cavity. A surface of at least a part of the permanent magnet disposed in the cavity is fixed to both of the bottom surface and the side surface through an adhesive.
    Type: Application
    Filed: February 26, 2018
    Publication date: May 13, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tetsuya Ueda, Hironobu Shibata, Yukinobu Tarui, Hidenori Ishibashi
  • Patent number: 10944143
    Abstract: In a non-reciprocal circuit element, a permanent magnet is connected to one main surface of a magnetic plate, and a circuit board is connected to the other main surface of the magnetic plate, with a solder bump lying between the circuit board and the other main surface. The permanent magnet can control the transmission of electrical signal from each of a plurality of signal conductors of circuit board to a corresponding one of a plurality of input/output terminals of the magnetic plate. The non-reciprocal circuit element further includes an underfill material arranged between the magnetic plate and the circuit board. The magnetic plate has a through hole formed therein, the through hole extending from one main surface to the other main surface. The through hole has an empty space in which at least a part of a conductive film arranged in the through hole is exposed.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: March 9, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tetsuya Ueda, Hironobu Shibata, Yukinobu Tarui, Hidenori Ishibashi
  • Publication number: 20200118859
    Abstract: A process apparatus includes an electrostatic chuck disposed at a substrate holder. The electrostatic chuck includes a dielectric and an electrode. The electrode is disposed in an interior of the dielectric. The apparatus further includes a circuit electrically connected to the electrode of the electrostatic chuck and a first earth wire electrically connected to the circuit. The first earth wire is shielded by a metal with an electrically insulating cover interposed.
    Type: Application
    Filed: March 12, 2019
    Publication date: April 16, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroshi SANDA, Kai HU, Hironobu SHIBATA, Koji FUJIBAYASHI, Yoshikuni TATEYAMA, Hideto YABUI
  • Patent number: 10514135
    Abstract: A light emitting device includes a semiconductor laser element configured to emit a first light, a wavelength converting member configured to emit a second light upon being irradiated by the first light, and a support member defining a through-hole allowing an optical path of the first light to pass through. The through-hole is defined by, in order from a light incident side to a light emitting side with respect to the first light, a lower portion with opening width decreasing from the light incident side to the light emitting side, and an upper portion where the wavelength converting member is fixed. The semiconductor laser element is disposed at a location allowing the first light to enter the lower portion of the through-hole while also allowing a part of the first light to be reflected at a wall defining the lower portion of the through-hole.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: December 24, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Hironobu Shibata, Soichiro Miura, Takashi Namie
  • Publication number: 20190139702
    Abstract: An irreversible circuit element that can reduce manufacturing costs by preventing faults that lead to product defects includes a magnetic body, a magnetic body securing casing, and a magnet. The magnetic body securing casing is arranged so as to surround the magnetic body. The magnet is arranged on one side of the magnetic body. The magnetic body securing casing includes a first electrode on one casing main surface arranged on the one side, a second electrode on the other casing main surface arranged on the other side opposite to the one side, and a through-conductor that passes through the magnetic body securing casing and electrically connects the first electrode to the second electrode. The first electrode is connected to a first wiring arranged on the one side of the magnetic body.
    Type: Application
    Filed: November 4, 2016
    Publication date: May 9, 2019
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yoichi KITAMURA, Tetsuya UEDA, Hironobu SHIBATA, Yukinobu TARUI
  • Publication number: 20190123413
    Abstract: In a non-reciprocal circuit element, a permanent magnet is connected to one main surface of a magnetic plate, and a circuit board is connected to the other main surface of the magnetic plate, with a solder bump lying between the circuit board and the other main surface. The permanent magnet can control the transmission of electrical signal from each of a plurality of signal conductors of circuit board to a corresponding one of a plurality of input/output terminals of the magnetic plate. The non-reciprocal circuit element further includes an underfill material arranged between the magnetic plate and the circuit board. The magnetic plate has a through hole formed therein, the through hole extending from one main surface to the other main surface. The through hole has an empty space in which at least a part of a conductive film arranged in the through hole is exposed.
    Type: Application
    Filed: April 21, 2017
    Publication date: April 25, 2019
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tetsuya Ueda, Hironobu Shibata, Yukinobu Tarui, Hidenori Ishibashi
  • Publication number: 20180058642
    Abstract: A light emitting device includes a semiconductor laser element configured to emit a first light, a wavelength converting member configured to emit a second light upon being irradiated by the first light, and a support member defining a through-hole allowing an optical path of the first light to pass through. The through-hole is defined by, in order from a light incident side to a light emitting side with respect to the first light, a lower portion with opening width decreasing from the light incident side to the light emitting side, and an upper portion where the wavelength converting member is fixed. The semiconductor laser element is disposed at a location allowing the first light to enter the lower portion of the through-hole while also allowing a part of the first light to be reflected at a wall defining the lower portion of the through-hole.
    Type: Application
    Filed: August 16, 2017
    Publication date: March 1, 2018
    Inventors: Hironobu SHIBATA, Soichiro MIURA, Takashi NAMIE
  • Patent number: 9761922
    Abstract: Input/output terminals 6a, 6b and 6c are formed within portions of cutouts 5a, 5b and 5c provided in a ground conductor 5 on the underside of a magnetic material 3; signal conductors 9a, 9b and 9c are formed within portions of cutouts 8a, 8b and 8c provided in a ground conductor 8 on the top surface of a dielectric substrate 7 at the same places as the cutouts 5a, 5b and 5c of the ground conductor; through holes 10a, 10b and 10c electrically connect a center conductor 4 to the input/output terminals 6a, 6b and 6c; metal bumps 11a, 11b and 11c electrically connect the input/output terminals 6a, 6b and 6c to the signal conductors 9a, 9b and 9c facing each other; and metal bumps 16 electrically connect the ground conductor 5 to the ground conductor 8.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: September 12, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hidenori Ishibashi, Tetsu Owada, Akihiro Ando, Hironobu Shibata
  • Publication number: 20160211564
    Abstract: Input/output terminals 6a, 6b and 6c are formed within portions of cutouts 5a, 5b and 5c provided in a ground conductor 5 on the underside of a magnetic material 3; signal conductors 9a, 9b and 9c are formed within portions of cutouts 8a, 8b and 8c provided in a ground conductor 8 on the top surface of a dielectric substrate 7 at the same places as the cutouts 5a, 5b and 5c of the ground conductor; through holes 10a, 10b and 10c electrically connect a center conductor 4 to the input/output terminals 6a, 6b and 6c; metal bumps 11a, 11b and 11c electrically connect the input/output terminals 6a, 6b and 6c to the signal conductors 9a, 9b and 9c facing each other; and metal bumps 16 electrically connect the ground conductor 5 to the ground conductor 8.
    Type: Application
    Filed: October 6, 2014
    Publication date: July 21, 2016
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hidenori ISHIBASHI, Tetsu OWADA, Akihiro ANDO, Hironobu SHIBATA
  • Publication number: 20150262947
    Abstract: According to one embodiment, a semiconductor device includes first layer that includes a first metal element and a second layer that is provided on the first layer and includes the first metal element and a second metal element that is different from the first metal element. The semiconductor device also includes a solder layer that is provided on the second layer such that the second layer is between the first and solder layers. The solder layer includes the second metal element.
    Type: Application
    Filed: August 29, 2014
    Publication date: September 17, 2015
    Inventor: Hironobu SHIBATA
  • Patent number: 9041143
    Abstract: The semiconductor device includes a first semiconductor layer of the first conductive type, a second semiconductor layer having the cubic crystalline structure formed on the first semiconductor layer, an electrode formed on the second semiconductor layer, and a reactive region formed between the second semiconductor layer and the electrode. The second semiconductor layer includes an upper surface that is tilted from the (100) plane. The reactive region includes at least one element constituting the second semiconductor layer, at least one element constituting the electrode, and forming a protuberance extending toward the second semiconductor layer.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: May 26, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yukie Nishikawa, Nobuhiro Takahashi, Hironobu Shibata
  • Publication number: 20150069614
    Abstract: A semiconductor device includes a first metal layer disposed on a first surface of a semiconductor layer, or a portion thereof. The first metal layer is made of a first metal. At least a portion of the first metal layer is crystallized. A second metal layer is disposed on a second surface of the semiconductor layer. The second surface is opposite the first surface. The second metal layer is also made of the first metal and has at least a portion that is crystallized. In some embodiments, the first metal may be nickel. In some embodiments, the semiconductor device may be a power semiconductor device, such as an insulated gate bipolar transistor and a fast recovery diode.
    Type: Application
    Filed: February 28, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yukie NISHIKAWA, Hironobu SHIBATA, Nobuhiro TAKAHASHI
  • Publication number: 20150056727
    Abstract: A method of inspecting a semiconductor device includes attaching an inspection tool on a back surface of a semiconductor substrate including the semiconductor device, the inspection tool including a sheet and a holding frame, the sheet being larger than the semiconductor substrate and being provided with an opening in a center portion of the sheet, the opening being smaller than the semiconductor substrate, the holding frame holding an outer periphery of the sheet, and a supporting substrate being attached on a front surface of the semiconductor substrate, removing the supporting substrate attached on the front surface of the semiconductor substrate, and measuring electrical characteristics of the semiconductor device.
    Type: Application
    Filed: October 1, 2014
    Publication date: February 26, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Daisuke YAMASHITA, Hironobu SHIBATA, Akira EZAKI
  • Patent number: 8900962
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include forming a base region and an emitter region in a front surface of a semiconductor layer. The method can include forming a first impurity implantation region by implanting first impurity of a first conductivity type into a back surface of the semiconductor layer. The method can include selectively forming a second impurity implantation region by selectively implanting second impurity of a second conductivity type into the first impurity implantation region. In addition, the method can include irradiating the first impurity implantation region and the second impurity implantation region with laser light. A peak of impurity concentration profile in a depth direction of at least one of the first impurity implantation region and the second impurity implantation region before irradiation with the laser light is adjusted to a depth of 0.05 ?m or more and 0.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: December 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Yamashita, Etsuo Hamada, Hideki Nozaki, Hironobu Shibata
  • Publication number: 20140284755
    Abstract: The semiconductor device includes a first semiconductor layer of the first conductive type, a second semiconductor layer having the cubic crystalline structure formed on the first semiconductor layer, an electrode formed on the second semiconductor layer, and a reactive region formed between the second semiconductor layer and the electrode. The second semiconductor layer includes an upper surface that is tilted from the (100) plane. The reactive region includes at least one element constituting the second semiconductor layer, at least one element constituting the electrode, and forming a protuberance extending toward the second semiconductor layer.
    Type: Application
    Filed: September 3, 2013
    Publication date: September 25, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yukie NISHIKAWA, Nobuhiro TAKAHASHI, Hironobu SHIBATA
  • Publication number: 20130249063
    Abstract: An aspect of the present embodiment, there is provided a shield plate configured to cover a semiconductor substrate including a semiconductor device in which a first semiconductor element and a second semiconductor element are included, in implanting charged particles into the semiconductor substrate to provide a lifetime control layer in the semiconductor substrate, including, an alignment mark configured to align with respect to a semiconductor substrate, a first region configured to cover the first semiconductor element, and a second region configured to cover the second semiconductor element, a thickness of the second region being thinner than a thickness of the first region.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 26, 2013
    Inventors: Hironobu SHIBATA, Etsuo HAMADA
  • Publication number: 20130244351
    Abstract: An aspect of one embodiment, there is provided a method of inspecting a semiconductor device, attaching an inspection tool on a back surface of a semiconductor substrate, the inspection tool including a sheet and a holding frame, the sheet being larger than the semiconductor substrate and being provided an opening in a center portion of the sheet, the opening being smaller than the semiconductor substrate, the holding frame holding an outer periphery of the sheet, a supporting substrate being attached on a front surface of the semiconductor substrate, removing the supporting substrate attached on the front surface of the semiconductor substrate, and inspecting electrical characteristics of the semiconductor substrate.
    Type: Application
    Filed: February 28, 2013
    Publication date: September 19, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Daisuke YAMASHITA, Hironobu SHIBATA, Akira EZAKI