Abstract: A semiconductor integrated circuit device according to the present invention includes a booster circuit 1 for raising an external power supply voltage Vccext, a level detecting circuit 2 for detecting fluctuation in a stepped-up voltage Vccint2, an internal voltage generating circuit 3 for generating an internal voltage Vccint on the basis of the stepped-up voltage Vccint2, an address buffer 4, an address decoder 5, and a memory cell array 6 of an EEPROM structure. The level detecting circuit 2 includes a first level detecting part for performing level detection during a memory access state, and a second level detecting part for performing level detection during a stand-by state. During the stand-by state, the internal voltage generating circuit 3 short-circuits the stepped-up voltage Vccint2 and the internal voltage Vccint.

Abstract: A differential amplifier comprises an n-channel MOS transistor to the gate of which an input voltage VIN1 is fed, and an n-channel MOS transistor to the gate of which an input voltage VIN2 is fed. A p-channel MOS transistor arranged in such a manner that, to the source thereof, a power source voltage Vcc is fed, and the gate and drain thereof are connected to the drain of the MOS transistor, and a p-channel MOS transistor arranged in such a manner that the gate thereof is connected to the drain of the MOS transistor, the drain thereof is connected to the drain of the MOS transistor, and the voltage at this drain is outputted as an output voltage VOUT, and the output current I of a constant-current source is set so that the transistors constituting a differential amplifier may operate in a weak inversion zone.

Abstract: A negative voltage detection circuit has a detection level of which is independent from the threshold voltage of a MOS transistor incorporated into the memory device. The negative voltage detection circuit detects whether or not the output voltage of a charge pump has a desired level, and then a signal is output in accordance with the detection result. The negative voltage detection circuit detects the negative voltage by comparing the multiple of the negative voltage by -(1/n) (n is a natural number) with a the positive inner reference voltage V.sub.ref. When the multiple and the reference voltage V.sub.ref are equal to each other, the negative voltage detection circuit determines that the negative voltage has the desired level. When the level of the output is lower than the desired level, the charge pump is stopped. Otherwise, a control signal is output to operate the charge pump so as to control the negative voltage at the desired level by the feed back control.

Abstract: A semiconductor memory device is provided which incorporates a voltage generation circuit capable of generating a high voltage even when a low power voltage is applied to the device. To control the gate voltage of each cell included in a memory cell array, a negative voltage generating circuit connected to a row decoder is included in a boosting circuit. In the case of using a single power of a low voltage, the negative voltage generating circuit generates a negative high voltage during, for example, data erasing. The gate of each P-channel MOS transistor for data transfer is supplied with a pulse signal with an amplitude based on a voltage VCCH which is higher than an external power voltage VCC and obtained by boosting the voltage VCC. As a result, a high voltage can be transferred and output efficiently even if the external power voltage is low.

Abstract: A decoder circuit selectively controls the transfer gate group. The transfer gate group is stacked so as to form a tree structure having multiple stages of transfer gates and enable a monitoring bus line to be connected to any column in a memory cell array. This configuration enables the current in each memory cell to be monitored at an external pad via a single bus line, which reduces the area occupied by the bus lines, suppressing an increase in the chip size.

Abstract: A nonvolatile semiconductor memory device includes a row decoder circuit having first and second N-channel MOS transistors and first and second P-channel MOS transistors which correspond to each of word lines. One end of a source-to-drain current path of the first N-channel MOS transistor is connected to the word line, and the other end thereof is connected to a corresponding one of output terminals of a predecoder circuit. One end of a source-to-drain current path of the second N-channel MOS transistor is connected to the word line, and the other end thereof is supplied with a voltage of 0 V or more in a data erase mode and is supplied with a low logical level signal in modes other than the data erase mode.

Abstract: A pull-up P-channel MOS transistor is connected between an output node and a VPP power supply terminal, while a pull-down N-channel MOS transistor is connected between the output node and a VSS power supply terminal. The output node has been electrically charged to VPP in an initial state. When a control signal SAEN has been made to be the "L" level, the change in the output node is gradually discharged. Since the output from the differential amplifying circuit is at the "H" level, the voltage at the output node is rapidly lowered. When the voltage at the output node has been made to be lower than a predetermined level, output voltage VOUT having a predetermined level is output.

Abstract: A semiconductor circuit device includes an oscillator for outputting an oscillating signal, a driving signal generator for generating driving signals having respective phases based on a counting of oscillations of the oscillating signal, and a charge pump circuit driven by the driving signals. A pulse width ratio of the driving signals to one another is constant even when an oscillation period of the oscillating signal output by the oscillator changes, whereby the charge pump operates properly under changing conditions.

Abstract: A memory cell array has a plurality of memory cells formed of EEPROM cells arranged in a matrix form. Data in the memory cells is flash-erased, and after this, word lines other than a selected word line are set to a negative potential and erasing verification for detecting an insufficiently erased memory cell is effected. The flash-erasing and erasing verification are repeatedly effected until no insufficiently erased memory cell is detected. When no insufficiently erased memory cell is detected, word lines other than a selected word line are set to a negative potential and an overerased memory cell is detected. When an overerased memory cell is detected, weak program is effected for the cell by applying a voltage lower than the normal writing voltage to the cell.

Abstract: A semiconductor integrated circuit device includes a test mode setting circuit. The test mode setting circuit includes an AND circuit for deriving the logical AND of a test mode setting permission signal and a signal input from a pin, and a latch circuit which is set by an output of the AND circuit and reset by a test mode setting release signal. After the test content is latched in the latch circuit in response to a test mode setting permission signal, the test is effected according to the setting of state of the semiconductor integrated circuit device and data latched in the latch circuit.

Abstract: A data latch circuit comprises a non-volatile memory cell having its threshold voltage changed in accordance with data to be stored therein, and a latch circuit. The cell has a transistor for writing data and a transistor for reading data. The writing and reading transistors has a common floating gate. The reading transistor has a threshold voltage lower than the writing transistor. During normal operation, a ground potential is applied to the control gate of the reading transistor. The latch circuit latches data in accordance with whether the non-volatile memory cell is in the on-state or off-state.

Abstract: A data latch circuit comprises a non-volatile memory cell having its threshold voltage changed in accordance with data to be stored therein, and a latch circuit. The cell has a transistor for writing data and a transistor for reading data. The writing and reading transistors has a common floating gate. The reading transistor has a threshold voltage lower than the writing transistor. During normal operation, a ground potential is applied to the control gate of the reading transistor. The latch circuit latches data in accordance with whether the non-volatile memory cell is in the on-state or off-state.

Abstract: A write control circuit is provided for supplying a gate of an n-channel enhancement-type writing transistor with a voltage corresponding to data when the data is written. The circuit comprises a reference potential-generation circuit, a differential amplifier, and a feedback circuit. The reference potential-generation circuit generates a reference potential substantially equal to the upper limit of that high level of each of the bit lines which is assumed at the time of writing. The differential amplifier has an input terminal to be supplied with the reference potential. A write voltage serving as an operation voltage is applied to the amplifier. The feedback circuit is connected between the other input terminal and output terminal of the differential amplifier.