Patents by Inventor Hiroshi Akamatsu
Hiroshi Akamatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210233581Abstract: Methods, apparatuses, and systems related to a memory device are described. The memory device may include local latching circuits each having a retention circuit and a driving circuit. The retention circuit may be configured to provide local storage of broadcasted information for a down-stream circuit. The driving circuit may be configured to connect a first voltage and a second voltage to the retention circuit at different times across the broadcast and the local storage.Type: ApplicationFiled: January 28, 2020Publication date: July 29, 2021Inventors: Yuan He, Hiroshi Akamatsu
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Publication number: 20210203316Abstract: Devices for generating a delay output signal are disclosed. A device may include a first delay circuit and a second delay circuit coupled in series between a first node and a second node in a delay path for the device, and having a third node therebetween. The device may also include a third circuit coupled to the third node and configured to charge the third node responsive to detecting a signal has passed through the first node and the third node. Associated semiconductor devices and methods are also disclosed.Type: ApplicationFiled: March 15, 2021Publication date: July 1, 2021Inventors: Hiroshi Akamatsu, Zhi Qi Huang
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Publication number: 20210183568Abstract: An onboard power supply device includes capacitors, a holder holding the capacitors, a mounting board having the capacitors mounted thereon and having the holder fixed thereto, and a heat-generating component mounted on the mounting board. Each of the capacitors includes a capacitor body and a lead terminal extending from the capacitor body. The holder includes a base part, first holding parts bundled by the base part and holding the capacitors, second holding parts each connected to a corresponding one of the first holding parts, and a fixing part extending from an outer edge of the base part toward the mounting board and fixed to the mounting board. The capacitor body of each of the capacitors is held by a corresponding one of the first holding parts. The lead terminal of each of the capacitors is held by a corresponding one of the second holding parts. The mounting board has a through-hole therein through which the lead terminal passes. The through-hole is connected to the lead terminal.Type: ApplicationFiled: November 18, 2019Publication date: June 17, 2021Inventors: MASASHI KANAYAMA, HIROSHI AKAMATSU, YUJI DOI, KATSUNORI ATAGO, HIROKI NISHINAKA, YOUICHI KAGEYAMA
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Patent number: 11011212Abstract: Methods, systems, and devices for delay calibration oscillators for a memory device are described. In some examples, a memory device may include a delay chain operable (e.g., for a calibration operation) in a ring oscillator configuration that includes a pulse generator. The pulse generator may be configured to output a pulse signal responsive to a transition of an input signal. By generating a pulse signal in a feedback loop of a ring oscillator, the ring oscillator may support a cycle that does not rely on both a first transition propagation pass (e.g., a rising edge propagation) and a responsive, opposite transition propagation pass (e.g., a falling edge propagation) through the delay chain, which may support a ring oscillator cycle time (e.g., period) that more closely represents aspects of the delay chain that are meant to be calibrated.Type: GrantFiled: May 12, 2020Date of Patent: May 18, 2021Assignee: Micron Technology, Inc.Inventor: Hiroshi Akamatsu
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Patent number: 10998893Abstract: Methods and apparatus for generating a delayed output signal from an input signal applied to an RC delay circuit of a semiconductor device during an active mode. The RC delay circuit is configured to pull up a voltage level on a node responsive to a reset signal during a stand-by mode.Type: GrantFiled: August 1, 2018Date of Patent: May 4, 2021Assignee: Micron Technology, Inc.Inventors: Hiroshi Akamatsu, Zhi Qi Huang
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Patent number: 10978130Abstract: Methods, systems, and devices for temperature-based access timing for a memory device are described. In some memory devices, accessing memory cells may be associated with different operations that are variously dependent on a temperature of the memory device. For example, some operations associated with accessing a memory cell may have a longer duration and others a shorter duration depending on the temperature of the memory device. In accordance with examples as disclosed herein, a memory device may be configured for performing some portions of an access operation according to a duration that is proportional to a temperature of the memory device, and performing other portions of the access operation according to a duration that is inversely proportional to a temperature of the memory device.Type: GrantFiled: March 25, 2020Date of Patent: April 13, 2021Assignee: Micron Technology, Inc.Inventors: Victor Wong, Sihong Kim, Hiroshi Akamatsu, Daniele Vimercati, John D. Porter
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Publication number: 20210065786Abstract: Latch circuitry configured to latch data for use in the memory device. The latch circuitry includes latch cells each configured to store a bit of the data. The latch circuitry also includes a data line coupled to a first side of the latch cells and a data false line coupled to a second side of the latch cells. The latch circuitry also includes a write driver that includes an input configured to receive the data to be stored in the latch cells and a pair of inverters coupled to the input and configured to output a data signal to a first side of the latch cells. The latch circuitry also includes an inverter coupled to the input and configured to generate a data false signal to a second side of the latch cells. The data used to generate the data false signal is not passed through the pair of inverters.Type: ApplicationFiled: July 13, 2020Publication date: March 4, 2021Inventors: Hiroshi Akamatsu, Simon J. Lovett
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Patent number: 10937515Abstract: Fuse latch circuits and related systems, methods, and apparatuses are disclosed. An apparatus includes a half interlock latch circuit including a first half and a second half. The first half of the half interlock latch circuit is configured to operate in a high impedance state responsive to operation of the second half of the half interlock latch circuit in a driven state. The second half of the half interlock latch circuit is configured to operate in a high impedance state responsive to operation of the first half of the half interlock latch circuit in a driven state.Type: GrantFiled: February 19, 2020Date of Patent: March 2, 2021Assignee: Micron Technology, Inc.Inventors: Yuan He, Hiroshi Akamatsu
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Publication number: 20210046673Abstract: Provided is a magnetic clamp device that is capable of more finely measuring an induced voltage generated in a coil and selecting countermeasures against reductions in magnetization force. Multiple magnet blocks 11, 21 each comprising an invertible magnet 18, the polarity of which can be inverted, and non-invertible magnet 15, are positioned on a surface of a plate PL composed of magnetic body magnetically clamping a mold M1, M2 when in a magnetized state. The magnetic flux traversing the invertible magnet 18; and a control device 33 that determines whether or not there has been a polarity inversion in the induced voltage detected from the coil 31, and if there has been a polarity inversion, warns that the adhesion of the molds M1, M2 has decreased.Type: ApplicationFiled: April 1, 2019Publication date: February 18, 2021Inventors: HIROSHI AKAMATSU, MASAKAZU YOSHIDA, SHOTARO MURATA, IKKYU ODA
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Publication number: 20210044296Abstract: Methods, systems, and devices for leakage current reduction in electronic devices are described. Electronic devices may be susceptible to leakage currents when operating in a first mode, such as an inactive (e.g., a standby) mode. To mitigate leakage current, an electronic device may include transistors coupled in cascode configuration where a gate of a drain-side transistor in the cascode configuration is configured to be biased by an adjustable (e.g., a dynamic) control signal. When the transistors are inactive (e.g., “off”), the control signal may be adjusted to prevent leakage associated with the inactive transistors. Further, a source-side transistor in the cascode configuration may be configured to have a high threshold voltage (e.g., relative to the drain-side transistor).Type: ApplicationFiled: October 23, 2020Publication date: February 11, 2021Inventors: Hiroshi Akamatsu, Ki-Jun Nam, John David Porter
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Patent number: 10867660Abstract: An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit includes a first defective address storing circuit and a first detection circuit. The first defective address storing circuit stores first enable information along with first defective address. The first enable information indicates whether or not the second word line is functional. The first detection circuit provides a first signal when the first word line is accessed. The first signal indicates whether or not the second word line is functional. The control circuit activates the second word line when the first signal indicates that the second word line is functional and does not activate the second word line when the first signal indicates that the second word line is not functional.Type: GrantFiled: February 21, 2020Date of Patent: December 15, 2020Assignee: Micron Technology, Inc.Inventor: Hiroshi Akamatsu
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Patent number: 10848153Abstract: Methods, systems, and devices for leakage current reduction in electronic devices are described. Electronic devices may be susceptible to leakage currents when operating in a first mode, such as an inactive (e.g., a standby) mode. To mitigate leakage current, an electronic device may include transistors coupled in cascode configuration where a gate of a drain-side transistor in the cascode configuration is configured to be biased by an adjustable (e.g., a dynamic) control signal. When the transistors are inactive (e.g., “off”), the control signal may be adjusted to prevent leakage associated with the inactive transistors. Further, a source-side transistor in the cascode configuration may be configured to have a high threshold voltage (e.g., relative to the drain-side transistor).Type: GrantFiled: November 30, 2018Date of Patent: November 24, 2020Assignee: Micron Technology, Inc.Inventors: Hiroshi Akamatsu, Ki-Jun Nam, John David Porter
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Publication number: 20200304113Abstract: Methods and apparatus for generating a delayed output signal from an input signal applied to an RC delay circuit of a semiconductor device during an active mode. The RC delay circuit is configured to pull up a voltage level on a node responsive to a reset signal during a stand-by mode.Type: ApplicationFiled: August 1, 2018Publication date: September 24, 2020Inventors: Hiroshi Akamatsu, Zhi Qi Huang
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Patent number: 10734067Abstract: Latch circuitry configured to latch data for use in the memory device. The latch circuitry includes latch cells each configured to store a bit of the data. The latch circuitry also includes a data line coupled to a first side of the latch cells and a data false line coupled to a second side of the latch cells. The latch circuitry also includes a write driver that includes an input configured to receive the data to be stored in the latch cells and a pair of inverters coupled to the input and configured to output a data signal to a first side of the latch cells. The latch circuitry also includes an inverter coupled to the input and configured to generate a data false signal to a second side of the latch cells. The data used to generate the data false signal is not passed through the pair of inverters.Type: GrantFiled: August 26, 2019Date of Patent: August 4, 2020Assignee: Micron Technology, Inc.Inventors: Hiroshi Akamatsu, Simon J. Lovett
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Publication number: 20200194050Abstract: An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit includes a first defective address storing circuit and a first detection circuit. The first defective address storing circuit stores first enable information along with first defective address. The first enable information indicates whether or not the second word line is functional. The first detection circuit provides a first signal when the first word line is accessed. The first signal indicates whether or not the second word line is functional. The control circuit activates the second word line when the first signal indicates that the second word line is functional and does not activate the second word line when the first signal indicates that the second word line is not functional.Type: ApplicationFiled: February 21, 2020Publication date: June 18, 2020Applicant: MICRON TECHNOLOGY, INC.Inventor: Hiroshi Akamatsu
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Publication number: 20200177184Abstract: Methods, systems, and devices for leakage current reduction in electronic devices are described. Electronic devices may be susceptible to leakage currents when operating in a first mode, such as an inactive (e.g., a standby) mode. To mitigate leakage current, an electronic device may include transistors coupled in cascode configuration where a gate of a drain-side transistor in the cascode configuration is configured to be biased by an adjustable (e.g., a dynamic) control signal. When the transistors are inactive (e.g., “off”), the control signal may be adjusted to prevent leakage associated with the inactive transistors. Further, a source-side transistor in the cascode configuration may be configured to have a high threshold voltage (e.g., relative to the drain-side transistor).Type: ApplicationFiled: November 30, 2018Publication date: June 4, 2020Inventors: Hiroshi Akamatsu, Ki-Jun Nam, John David Porter
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Patent number: 10607686Abstract: An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit includes a first defective address storing circuit and a fast detection circuit. The first defective address storing circuit stores first enable information along with first defective address. The first enable information indicates whether or not the second word line is functional. The first detection circuit provides a first signal when the first word line is accessed. The first signal indicates whether or not the second word line is functional. The control circuit activates the second word line when the first signal indicates that the second word line is functional and does not activate the second word line when the first signal indicates that the second word line is not functional.Type: GrantFiled: August 24, 2018Date of Patent: March 31, 2020Assignee: Micron Technology, Inc.Inventor: Hiroshi Akamatsu
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Patent number: 10186363Abstract: A magnetic component unit in the present disclosure includes: a coil component; a heat dissipator which has an engagement fixing portion and a press fixing portion; and a magnetic core fixing portion. The magnetic core fixing portion includes: a holding portion that presses against the coil component; an engaging portion that extends from a first end part of the holding portion toward the heat dissipator and has a turned-back end part; and a pressing portion that extends from a second end part of the holding portion toward the heat dissipator and has an end part bent into an L-shape. The engagement fixing portion has a U-shape, and one end and the other end of the engagement fixing portion are connected to a peripheral edge portion of the heat dissipator. The press fixing portion has a columnar shape and is provided vertically protruding from the heat dissipator.Type: GrantFiled: January 8, 2016Date of Patent: January 22, 2019Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Mitsuhiro Matsuo, Hiroshi Akamatsu
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Publication number: 20190013059Abstract: An apparatus includes, a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit includes a first defective address storing circuit and a fast detection circuit. The first defective address storing circuit stores first enable information along with first defective address. The first enable information indicates whether or not the second word line is functional. The first detection circuit provides a first signal when the first word line is accessed. The first signal indicates whether or not the second word line is functional. The control circuit activates the second word line when the first signal indicates that the second word line is functional and does not activate the second word line when the first signal indicates that the second word line is not functional.Type: ApplicationFiled: August 24, 2018Publication date: January 10, 2019Applicant: Micron Technology, Inc.Inventor: Hiroshi Akamatsu
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Patent number: 10153031Abstract: An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit includes a first defective address storing circuit and a first detection circuit. The first defective address storing circuit stores first enable information along with first defective address. The first enable information indicates whether or not the second word line is functional. The first detection circuit provides a first signal when the first word line is accessed. The first signal indicates whether or not the second word line is functional. The control circuit activates the second word line when the first signal indicates that the second word line is functional and does not activate the second word line when the first signal indicates that the second word line is not functional.Type: GrantFiled: February 5, 2018Date of Patent: December 11, 2018Assignee: Micron Technology, Inc.Inventor: Hiroshi Akamatsu