Patents by Inventor Hiroshi Akamatsu
Hiroshi Akamatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10074443Abstract: Disclosed here is a semiconductor device that comprises plurality of input nodes configured to be supplied with input signals, a decoder coupled to the input nodes, the decoder configured to decode the input signals and output decoded sepals, and a plurality of fuse circuits provided correspondingly with the decoded signals and configured to be programmed responsive to the decoded signals, respectivelyType: GrantFiled: November 17, 2017Date of Patent: September 11, 2018Assignee: Micron Technology, Inc.Inventor: Hiroshi Akamatsu
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Publication number: 20180158504Abstract: An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit includes a first defective address storing circuit and a first detection circuit. The first defective address storing circuit stores first enable information along with first defective address. The first enable information indicates whether or not the second word line is functional. The first detection circuit provides a first signal when the first word line is accessed. The first signal indicates whether or not the second word line is functional. The control circuit activates the second word line when the first signal indicates that the second word line is functional and does not activate the second word line when the first signal indicates that the second word line is not functional.Type: ApplicationFiled: February 5, 2018Publication date: June 7, 2018Applicant: Micron Technology, Inc.Inventor: Hiroshi Akamatsu
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Patent number: 9922694Abstract: An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit includes a first defective address storing circuit and a first detection circuit. The first defective address storing circuit stores first enable information along with first defective address. The first enable information indicates whether or not the second word line is functional. The first detection circuit provides a first signal when the first word line is accessed. The first signal indicates whether or not the second word line is functional. The control circuit activates the second word line when the first signal indicates that the second word line is functional and does not activate the second word line when the first signal indicates that the second word line is not functional.Type: GrantFiled: May 15, 2015Date of Patent: March 20, 2018Assignee: Micron Technology, Inc.Inventor: Hiroshi Akamatsu
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Publication number: 20180075922Abstract: Disclosed here is a semiconductor device that comprises plurality of input nodes configured to be supplied with input signals, a decoder coupled to the input nodes, the decoder configured to decode the input signals and output decoded sepals, and a plurality of fuse circuits provided correspondingly with the decoded signals and configured to be programmed responsive to the decoded signals, respectivelyType: ApplicationFiled: November 17, 2017Publication date: March 15, 2018Applicant: MICRON TECHNOLOGY, INC.Inventor: HIROSHI AKAMATSU
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Publication number: 20180019047Abstract: A magnetic component unit in the present disclosure includes: a coil component; a heat dissipator which has an engagement fixing portion and a press fixing portion; and a magnetic core fixing portion. The magnetic core fixing portion includes: a holding portion that presses against the coil component; an engaging portion that extends from a first end part of the holding portion toward the heat dissipator and has a turned-back end part; and a pressing portion that extends from a second end part of the holding portion toward the heat dissipator and has an end part bent into an L-shape. The engagement fixing portion has a U-shape, and one end and the other end of the engagement fixing portion are connected to a peripheral edge portion of the heat dissipator. The press fixing portion has a columnar shape and is provided vertically protruding from the heat dissipator.Type: ApplicationFiled: January 8, 2016Publication date: January 18, 2018Inventors: Mitsuhiro MATSUO, Hiroshi AKAMATSU
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Patent number: 9865359Abstract: Disclosed here is a semiconductor device that comprises a plurality of input nodes configured to be supplied with input signals, a decoder coupled to the input nodes, the decoder configured to decode the input signals and output decoded signals, and a plurality of fuse circuits provided correspondingly with the decoded signals and configured to be programmed responsive to the decoded signals, respectively.Type: GrantFiled: July 17, 2017Date of Patent: January 9, 2018Assignee: Micron Technology, Inc.Inventor: Hiroshi Akamatsu
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Publication number: 20170316836Abstract: Disclosed here is a semiconductor device that comprises a plurality of input nodes configured to be supplied with input signals, a decoder coupled to the input nodes, the decoder configured to decode the input signals and output decoded signals, and a plurality of fuse circuits provided correspondingly with the decoded signals and configured to be programmed responsive to the decoded signals, respectively.Type: ApplicationFiled: July 17, 2017Publication date: November 2, 2017Applicant: MICRON TECHNOLOGY, INC.Inventor: HIROSHI AKAMATSU
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Patent number: 9741447Abstract: Disclosed here is a semiconductor device that comprises a plurality of input nodes configured to be supplied with input signals, a decoder coupled to the input nodes, the decoder configured to decode the input signals and output decoded signals, and a plurality of fuse circuits provided correspondingly with the decoded signals and configured to be programmed responsive to the decoded signals, respectively.Type: GrantFiled: April 9, 2015Date of Patent: August 22, 2017Assignee: Micron Technology, Inc.Inventor: Hiroshi Akamatsu
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Publication number: 20150340077Abstract: An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit includes a first defective address storing circuit and a first detection circuit. The first defective address storing circuit stores first enable information along with first defective address. The first enable information indicates whether or not the second word line is functional. The first detection circuit provides a first signal when the first word line is accessed. The first signal indicates whether or not the second word line is functional. The control circuit activates the second word line when the first signal indicates that the second word line is functional and does not activate the second word line when the first signal indicates that the second word line is not functional.Type: ApplicationFiled: May 15, 2015Publication date: November 26, 2015Inventor: HIROSHI AKAMATSU
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Publication number: 20150310926Abstract: Disclosed here is a semiconductor device that comprises a plurality of input nodes configured to be supplied with input signals, a decoder coupled to the input nodes, the decoder configured to decode the input signals and output decoded signals, and a plurality of fuse circuits provided correspondingly with the decoded signals and configured to be programmed responsive to the decoded signals, respectively.Type: ApplicationFiled: April 9, 2015Publication date: October 29, 2015Inventor: HIROSHI AKAMATSU
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Publication number: 20140233334Abstract: A device includes a command decoder that is configured to output, in a normal operation mode, a precharge signal in response to a first type transition edge of a synchronous signal, and an active signal in response to a next first type transition edge that is next to the first type transition edge. The command decoder is configured to output, in a test mode, the precharge signal in response to a second type transition edge of the synchronous signal, and the active signal in response to a next first type transition edge that is next to the second type transition edge.Type: ApplicationFiled: April 28, 2014Publication date: August 21, 2014Applicant: Elpida Memory, Inc.Inventors: Kinu MATSUNAGA, Hiroshi AKAMATSU
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Publication number: 20140226423Abstract: Provided is a device, including: a first terminal which receives an external clock signal; a clock generation circuit connected to the first terminal to generate an internal clock signal based on the external clock signal; word lines and bit lines; amplifier circuits connected to the bit lines, respectively; and a control unit. The control unit controls, in a test operation, at least one of the word lines to repeat a selected state and an unselected state in accordance with the internal clock signal during a first period, and maintains the amplifier circuits in an active state during the first period. The control unit further controls, in a normal operation, the amplifier circuits to switch between the active state and an inactive state depending on switching between the selected state and the unselected state of the at least one of the word lines.Type: ApplicationFiled: April 18, 2014Publication date: August 14, 2014Applicant: Elpida Memory, Inc.Inventors: Hiroshi AKAMATSU, Shoji Kaneko
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Patent number: 8737158Abstract: A device includes a command decoder that is configured to output, in a normal operation mode, a precharge signal in response to a first type transition edge of a synchronous signal, and an active signal in response to a next first type transition edge that is next to the first type transition edge. The command decoder is configured to output, in a test mode, the precharge signal in response to a second type transition edge of the synchronous signal, and the active signal in response to a next first type transition edge that is next to the second type transition edge.Type: GrantFiled: March 27, 2012Date of Patent: May 27, 2014Inventors: Kinu Matsunaga, Hiroshi Akamatsu
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Patent number: 8730742Abstract: Provided is a device, including: a first terminal which receives an external clock signal; a clock generation circuit connected to the first terminal to generate an internal clock signal based on the external clock signal; word lines and bit lines; amplifier circuits connected to the bit lines, respectively; and a control unit. The control unit controls, in a test operation, at least one of the word lines to repeat a selected state and an unselected state in accordance with the internal clock signal during a first period, and maintains the amplifier circuits in an active state during the first period. The control unit further controls, in a normal operation, the amplifier circuits to switch between the active state and an inactive state depending on switching between the selected state and the unselected state of the at least one of the word lines.Type: GrantFiled: April 10, 2012Date of Patent: May 20, 2014Inventors: Hiroshi Akamatsu, Shoji Kaneko
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Publication number: 20120262996Abstract: Provided is a device, including: a first terminal which receives an external clock signal; a clock generation circuit connected to the first terminal to generate an internal clock signal based on the external clock signal; word lines and bit lines; amplifier circuits connected to the bit lines, respectively; and a control unit. The control unit controls, in a test operation, at least one of the word lines to repeat a selected state and an unselected state in accordance with the internal clock signal during a first period, and maintains the amplifier circuits in an active state during the first period. The control unit further controls, in a normal operation, the amplifier circuits to switch between the active state and an inactive state depending on switching between the selected state and the unselected state of the at least one of the word lines.Type: ApplicationFiled: April 10, 2012Publication date: October 18, 2012Applicant: Elpida Memory, Inc.Inventors: Hiroshi AKAMATSU, Shoji KANEKO
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Publication number: 20120250435Abstract: A device includes a command decoder that is configured to output, in a normal operation mode, a precharge signal in response to a first type transition edge of a synchronous signal, and an active signal in response to a next first type transition edge that is next to the first type transition edge. The command decoder is configured to output, in a test mode, the precharge signal in response to a second type transition edge of the synchronous signal, and the active signal in response to a next first type transition edge that is next to the second type transition edge.Type: ApplicationFiled: March 27, 2012Publication date: October 4, 2012Applicant: ELPIDA MEMORY, INC.Inventors: Kinu MATSUNAGA, Hiroshi AKAMATSU
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Patent number: 7973298Abstract: A transport/storage cask for a radioactive material has an inner shell, an outer shell and a circular gamma ray shielding layer and a circular neutron shielding layer both of which are placed between the inner shell and the outer shell. The gamma ray shielding layer is formed by aligning a plurality of gamma ray shielding blocks composed of lead in a block shape in the circumferential direction. The entire gamma ray shielding block in the axial direction is covered with a copper tube having a higher elasticity limit than the gamma ray shielding block. In the above transport/storage cask, the gamma ray shielding layer composed of lead or a lead alloy is not easily deformed.Type: GrantFiled: August 4, 2008Date of Patent: July 5, 2011Assignee: Kobe Steel, Ltd.Inventors: Jun Shimojo, Hiroshi Akamatsu, Hiroaki Taniuchi, Kenichi Mantani
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Publication number: 20110133808Abstract: An apparatus has a delay circuit, a delay control circuit which detects the delay time of the delay circuit and generates a delay adjustment signal based upon the detection result, and a delay adjustment circuit operable to adjust delay time of the delay circuit in response to the delay adjustment signal.Type: ApplicationFiled: December 8, 2010Publication date: June 9, 2011Applicant: ELPIDA MEMORY, INC.Inventor: Hiroshi AKAMATSU
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Patent number: 7791402Abstract: An electrical fuse determination circuit that can speedily and reliably incorporate an electrical fuse data and improve a reliability of electrical fuse device, includes a first electrical fuse device of which one end connects with a higher voltage, a second electrical fuse device of which one end connects with a lower voltage, a set portion that puts one of the first electrical fuse device and the second electrical fuse device in a conductive state, and a determination portion that determines a voltage level of a predetermined contact point connecting the other end of the first electrical fuse device and the other end of the second electrical fuse device.Type: GrantFiled: October 30, 2008Date of Patent: September 7, 2010Assignee: Elpida Memory, Inc.Inventor: Hiroshi Akamatsu
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Publication number: 20100195416Abstract: An anti-fuse circuit uses first to fifth power supplies which have first to fifth power supply voltages, respectively, in the order of highest to lowest during writing. The anti-fuse circuit includes: a first level shift circuit which is connected to the second to fourth power supplies and which converts a first logic signal that changes between the third and fourth power supply voltages into a second logic signal that changes between the second and fourth power supply voltages; a second level shift circuit which is connected to the first, second, and fourth power supplies and which converts the second logic signal into a third logic signal that changes between the first and fourth power supply voltages; a transistor having a source connected to the first power supply and a gate connected to the third logic signal; and an anti-fuse element having one end connected to the drain of the transistor and the other end connected to the fifth power supply.Type: ApplicationFiled: February 1, 2010Publication date: August 5, 2010Applicant: Elpida Memory, Inc.Inventor: Hiroshi Akamatsu