Abstract: An electric connection inspection device includes: a cooling plate; an insulating plate provided on the cooling plate; a first measurement electrode provided on the insulating plate; and a second measurement electrode and a third measurement electrode provided above the first measurement electrode and located apart from the first measurement electrode. The insulating plate includes a variable thermal resistance mechanism. A semiconductor device can be installed between the first measurement electrode and the second measurement electrode and between the first measurement electrode and the third measurement electrode.

Abstract: In the present invention, in a FinFET having a channel forming region on a surface of a fin that is a semiconductor layer protruding on an upper surface of a substrate, a channel at a corner of the fin is prevented from becoming an ON state with a low voltage and a steep ON/OFF operation is made possible. As a means thereof, in a MOSFET that has a plurality of trenches, each of which have embedded therein a gate electrode, on an upper surface of an n-type epitaxial substrate provided with a drain region on a bottom surface and that has a channel region formed on a surface of a fin which is a protrusion part between the trenches adjacent to each other, a p-type body layer that constitutes a lateral surface of the fin, and a p+-type semiconductor region that constitutes a corner which is an end of the upper surface of the fin, are formed.

Abstract: Provided is a semiconductor device whose performance is improved. A p type body region is formed in an n type semiconductor layer containing silicon carbide, and a gate electrode is formed on the body region with a gate insulating film interposed therebetween. An n type source region is formed in the body region on a side surface side of the gate electrode, and the body region and a source region are electrically connected to a source electrode. A p type field relaxation layer FRL is formed in the semiconductor layer on the side surface side of the gate electrode, and the source electrode is electrically connected to the field relaxation layer FRL. The field relaxation layer FRL constitutes a part of the JFET 2Q which is a rectifying element, and a depth of the field relaxation layer FRL is shallower than a depth of the body region.

Abstract: When a cluster is configured by hypervisors of a plurality of servers, a shared storage including internal storages of the plurality of servers can be used. In a storage system in which a hypervisor managing VMs on each of the plurality of servers is included and the plurality of hypervisors configures a cluster, the plurality of servers each include a storage VM that provides the shared storage. One of the plurality of servers includes a manager VM that manages the hypervisors of the plurality of servers as the cluster. A virtual volume of the shared storage is provided as an LU for constructing the manager VM.

Abstract: Provided is a semiconductor device whose performance is improved. A p type body region is formed in an n type semiconductor layer containing silicon carbide, and a gate electrode is formed on the body region with a gate insulating film interposed therebetween. An n type source region is formed in the body region on a side surface side of the gate electrode, and the body region and a source region are electrically connected to a source electrode. A p type field relaxation layer FRL is formed in the semiconductor layer on the side surface side of the gate electrode, and the source electrode is electrically connected to the field relaxation layer FRL. The field relaxation layer FRL constitutes a part of the JFET 2Q which is a rectifying element, and a depth of the field relaxation layer FRL is shallower than a depth of the body region.

Abstract: A placing table structure according to an embodiment includes: a fixedly disposed refrigerated heat transfer element; a rotatable outer cylinder disposed around the refrigerated heat transfer element; and a stage connected to the outer cylinder and disposed above an upper surface of the refrigerated heat transfer element with inclusion of a gap between the refrigerated heat transfer element and the stage.

Abstract: A silicon carbide semiconductor device includes an n-type silicon carbide semiconductor substrate, a drain electrode electrically connected to a rear face, an n-type semiconductor layer having a second impurity concentration lower than the first impurity concentration, a p-type first semiconductor region, an n-type second semiconductor region, and an n-type third semiconductor region. A trench is formed having a gate electrode therein in which the bottom face of the trench contacts the p-type semiconductor region. A metal layer is electrically connected to the third semiconductor region, and a source electrode electrically connects the second semiconductor region and the metal layer to each other.

Abstract: An impedance matching method includes: calculating an output impedance of a theoretical circuit model set in advance from actual values of two variable components and a measured value of an input impedance; calculating values of the two variable components at the time of impedance matching through an arithmetic operation under a matching condition in the theoretical circuit model based on the calculated value of the output impedance assuming that the output impedance due to matching transition has the same value; and controlling the actual values of the variable components of the impedance matching device to correspond to the calculated two variable component values.

Abstract: An impedance matching method includes: calculating an output impedance of a theoretical circuit model set in advance from actual values of two variable components and a measured value of an input impedance; calculating values of the two variable components at the time of impedance matching through an arithmetic operation under a matching condition in the theoretical circuit model based on the calculated value of the output impedance assuming that the output impedance due to matching transition has the same value; and controlling the actual values of the variable components of the impedance matching device to correspond to the calculated two variable component values.

Abstract: An apparatus includes a row of substrate transfer devices 3 which can deliver a wafer W within a transfer chamber; and rows of process modules PM, arranged at right and left sides of the row of the substrate transfer devices along the row, configured to perform processes to the wafer W. The rows of the process modules PM are arranged such that each of the processes can be performed by at least two process modules PM. Thus, when a single process module PM cannot be used, the wafer W can be rapidly transferred to another process module PM which can perform the same process as performed in the corresponding process module. Therefore, even when the single process module PM cannot be used, the processes can be continued to the wafers W without stopping an operation of the apparatus, so that the number of wasted wafers W can be reduced.

Abstract: A silicon carbide semiconductor device includes an n-type silicon carbide semiconductor substrate, a drain electrode electrically connected to a rear face, an n-type semiconductor layer having a second impurity concentration lower than the first impurity concentration, a p-type first semiconductor region, an n-type second semiconductor region, an n-type third semiconductor region, a trench having a first side face and a second side face opposing to each other and a third side face intersecting with the first side face and the second side face, a gate electrode formed in the trench with a gate insulating film interposed therebetween, a metal layer electrically connected to the third semiconductor region, and a source electrode electrically connecting the second semiconductor region and the metal layer to each other.

Abstract: An apparatus includes a row of substrate transfer devices 3 which can deliver a wafer W within a transfer chamber; and rows of process modules PM, arranged at right and left sides of the row of the substrate transfer devices along the row, configured to perform processes to the wafer W. The rows of the process modules PM are arranged such that each of the processes can be performed by at least two process modules PM. Thus, when a single process module PM cannot be used, the wafer W can be rapidly transferred to another process module PM which can perform the same process as performed in the corresponding process module. Therefore, even when the single process module PM cannot be used, the processes can be continued to the wafers W without stopping an operation of the apparatus, so that the number of wasted wafers W can be reduced.

Abstract: An apparatus includes a row of substrate transfer devices 3 which can deliver a wafer W within a transfer chamber; and rows of process modules PM, arranged at right and left sides of the row of the substrate transfer devices along the row, configured to perform processes to the wafer W. The rows of the process modules PM are arranged such that each of the processes can be performed by at least two process modules PM. Thus, when a single process module PM cannot be used, the wafer W can be rapidly transferred to another process module PM which can perform the same process as performed in the corresponding process module. Therefore, even when the single process module PM cannot be used, the processes can be continued to the wafers W without stopping an operation of the apparatus, so that the number of wasted wafers W can be reduced.

Abstract: Provided is a technique of securing reliability of a gate insulating film, as much as in a Si power MOSFET, in a semiconductor device in which a semiconductor material having a larger band gap than silicon is used, and which is typified by, for example, an SiC power MOSFET. In order to achieve this object, in the in the SiC power MOSFET, the gate electrode GE is formed in contact with the gate insulating film GOX, and is formed of the polycrystalline silicon film PF1 having the thickness equal to or smaller than 200 nm, and the polycrystalline silicon film PF2 formed in contact with the polycrystalline silicon film PF1, and having any thickness.

Abstract: System and method of insulating film deposition. A sputter deposition chamber comprises a pair of targets made of the same insulating material. Each target is applied with a high frequency power signal concurrently. A phase adjusting unit is used to adjust the phase difference between the high frequency power signals supplied to the pair of targets to a predetermined value, thereby improving the in-plane thickness distribution of a resultant film. The predetermined value is target material specific.

Abstract: Provided is a technique of securing reliability of a gate insulating film, as much as in a Si power MOSFET, in a semiconductor device in which a semiconductor material having a larger band gap than silicon is used, and which is typified by, for example, an SiC power MOSFET. In order to achieve this object, in the in the SiC power MOSFET, the gate electrode GE is formed in contact with the gate insulating film GOX, and is formed of the polycrystalline silicon film PF1 having the thickness equal to or smaller than 200 nm, and the polycrystalline silicon film PF2 formed in contact with the polycrystalline silicon film PF1, and having any thickness.

Abstract: The network connection of a VM (target VM) that has been live-migrated from a first physical computer to a second physical computer is restored in a virtual computer system in which communication is performed using a certain type of information outside the jurisdiction of a virtualization mechanism. When receiving a packet from the VM, the first virtualization mechanism of the first physical computer extracts a certain type of information from the packet and registers the extracted certain type of information in a first management information unit. The first virtualization mechanism transmits the certain type of information in the first management information unit to the second virtualization mechanism of the second physical computer during live migration.

Abstract: A hypervisor as a movement source stores key information, and the key information is registered in a storage using the stored key information through a logical HBA which is used for migration.

Abstract: An apparatus includes a row of substrate transfer devices 3 which can deliver a wafer W within a transfer chamber; and rows of process modules PM, arranged at right and left sides of the row of the substrate transfer devices along the row, configured to perform processes to the wafer W. The rows of the process modules PM are arranged such that each of the processes can be performed by at least two process modules PM. Thus, when a single process module PM cannot be used, the wafer W can be rapidly transferred to another process module PM which can perform the same process as performed in the corresponding process module. Therefore, even when the single process module PM cannot be used, the processes can be continued to the wafers W without stopping an operation of the apparatus, so that the number of wasted wafers W can be reduced.

Abstract: A live migration in a virtual computer system. On a source physical computer, the control information area of the source logical FC-HBA (managed by an OS) is copied to the control information area of a dummy logical FC-HBA managed by a hypervisor. After an FC login to the dummy FC-HBA, an address conversion table is rewritten so that a host physical address for referring to the control information area of a logical HBA1? can be referred to using a guest logical address for referring to the control information area of the source FC-HBA. After the FC logout of the source FC-HBA, using a WWN of the FC used for the FC logout, a login to the destination logic FC-HBA is performed. Next, the OS on the source computer is taken over by the destination computer. Therefore, the disk accessed on the source computer can be accessed from the destination FC-HBA.