Patents by Inventor Hiroshi Miki

Hiroshi Miki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070094870
    Abstract: A receiving layer formed of a thermoplastic resin is softened by applying heat. By using a solvent containing conductive particles, an interconnect layer is formed on the receiving layer which is softened by the application of heat. The conductive particles are bonded together by heating the interconnect layer.
    Type: Application
    Filed: December 15, 2006
    Publication date: May 3, 2007
    Applicant: Seiko Epson Corporation
    Inventors: Tetsuya Otsuki, Hirofumi Kurosawa, Hiroshi Miki
  • Patent number: 7189598
    Abstract: A receiving layer is formed from a thermosetting resin precursor. An interconnecting layer is formed on the receiving layer from a dispersion liquid containing conductive particles. Heat is applied to the receiving layer and the interconnecting layer to cure the thermosetting resin precursor and to bond the conductive particles together.
    Type: Grant
    Filed: March 2, 2004
    Date of Patent: March 13, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Tetsuya Otsuki, Hirofumi Kurosawa, Hiroshi Miki
  • Publication number: 20060125048
    Abstract: An integrated semiconductor device comprising an analog integrated circuit or mixed signal integrated circuit having a capacitor, wherein the dielectric film of the capacitor is a laminated film consisting of a first dielectric film essentially composed of aluminum oxide and a second dielectric film essentially composed of crystallized niobium oxide. This integrated semiconductor device is small in size and has a low temperature coefficient and high reliability. The niobium oxide is crystallized to increase its dielectric constant and reduce its loss. To reduce the temperature coefficient, the film thickness ratio of the aluminum oxide layer to the niobium oxide layer is set to 0.2 to 1, preferably 0.4 to 0.7.
    Type: Application
    Filed: August 4, 2005
    Publication date: June 15, 2006
    Inventor: Hiroshi Miki
  • Patent number: 7034355
    Abstract: To achieve a higher operating speed, higher reliability, and lower power consumption by reducing the thickness of an inter-poly silicon insulator film between a floating gate and a control gate of a flash memory, a silicon dioxide film, a silicon nitride film, tantalum pentoxide, and a silicon dioxide film are formed in a multilayer structure to serve as the inter-poly insulator film between a floating gate and a control gate. With this configuration, tantalum pentoxide formed on the silicon nitride film has a dielectric constant of 50 or more, which is higher than that of the silicon dioxide film, and the thickness of the inter-poly silicon insulator film can be reduced.
    Type: Grant
    Filed: December 2, 2002
    Date of Patent: April 25, 2006
    Assignee: Renesas Technology Corp.
    Inventor: Hiroshi Miki
  • Publication number: 20050199490
    Abstract: A double-layer shutter control method of a multi-sputtering system provided with three targets in a single chamber and a double-layer rotating shutter mechanism having shutter plates which independently rotate and have holes formed therein, comprising selecting a target by a combination of holes of a first shutter plate and a second shutter plate and uses the selected target for a pre-sputtering step and a main sputtering step with continuous discharge so as to deposit a film on a substrate, whereby it is possible to prevent cross-contamination between targets due to target substances etc. deposited on the shutter plates.
    Type: Application
    Filed: March 14, 2005
    Publication date: September 15, 2005
    Applicant: ANELVA Corporation
    Inventors: Shuji Nomura, Ayumu Miyoshi, Hiroshi Miki
  • Publication number: 20050142742
    Abstract: A semiconductor device having a DRAM has a capacitor in which a dielectric film and an upper electrode are laminated on a lower electrode comprising a polysilicone, in which a natural oxide film oxidized by oxygen in the atmosphere grows to at least 1.5 nm on the surface of a lower electrode of the capacitor. Further, in forming the dielectric film, the dioxide film further grows in the case of using an oxidative raw material. This brings forth a reduction in capacitance, and an increase of a leakage current is caused. Therefore, after a dielectric film having a reduction property has been formed, the reduction property is promoted by a heat treatment to thereby reduce a dioxide film and realize making the dioxide film on the lower electrode surface thinner.
    Type: Application
    Filed: November 12, 2004
    Publication date: June 30, 2005
    Inventors: Osamu Tonomura, Hiroshi Miki, Yuichi Matsui, Tomoko Sekiguchi, Kikuo Watanabe
  • Publication number: 20050098813
    Abstract: Disclosed is herein a semiconductor device having a DRAM with less scattering of threshold voltage of MISFET in a memory cell and having good charge retainability of a capacitor, and a manufacturing method of the semiconductor device. An anti-oxidation film is formed to the side wall of a gate electrode before light oxidation thereby suppressing the oxidation of the side wall for the gate electrode and decreasing scattering of the thickness of the film formed to the sidewall in an asymmetric diffusion region structure in which the impurity concentration of an n-type semiconductor region and a p-type semiconductor region on the side of the data line is made relatively higher than the impurity concentration in the n-type semiconductor region and p-type semiconductor region on the side of the capacitor, respectively.
    Type: Application
    Filed: September 1, 2004
    Publication date: May 12, 2005
    Inventors: Tomoko Sekiguchi, Shinichiro Kimura, Renichi Yamada, Kikuo Watanabe, Hiroshi Miki, Kenichi Takeda
  • Publication number: 20050079662
    Abstract: To achieve a higher operating speed, higher reliability, and lower power consumption by reducing the thickness of an inter-poly silicon insulator film between a floating gate and a control gate of a flash memory, a silicon dioxide film, a silicon nitride film, tantalum pentoxide, and a silicon dioxide film are formed in a multilayer structure to serve as the inter-poly insulator film between a floating gate and a control gate. With this configuration, tantalum pentoxide formed on the silicon nitride film has a dielectric constant of 50 or more, which is higher than that of the silicon dioxide film, and the thickness of the inter-poly silicon insulator film can be reduced.
    Type: Application
    Filed: December 2, 2002
    Publication date: April 14, 2005
    Inventor: Hiroshi Miki
  • Publication number: 20050074936
    Abstract: A method of fabricating a semiconductor device, is provided including forming an insulating film having an opening portion on a substrate having a transistor, filling a conductive film in the opening portion, forming a reaction barrier film functioning to prevent a reaction on the insulating film, and forming a diffusion barrier film on the conductive film. Next a first electrode is formed on the diffusion barrier film, a ferroelectric film, including at least one element of the group consisting of lead, barium and bismuth is formed on the first electrode after the step of forming the reaction barrier film, and a second electrode is formed on the ferroelectric film.
    Type: Application
    Filed: October 20, 2004
    Publication date: April 7, 2005
    Inventors: Kazuyoshi Torii, Hiroshi Miki, Yoshihisa Fujisaki
  • Publication number: 20050051821
    Abstract: The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively acts as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.
    Type: Application
    Filed: August 18, 2004
    Publication date: March 10, 2005
    Inventors: Hiroshi Miki, Keiko Kushida, Yasuhiro Shimamoto, Shinichiro Takatani, Yoshihisa Fujisaki, Hiromi Nakai
  • Publication number: 20040241903
    Abstract: A receiving layer is formed from a thermosetting resin precursor. An interconnecting layer is formed on the receiving layer from a dispersion liquid containing conductive particles. Heat is applied to the receiving layer and the interconnecting layer to cure the thermosetting resin precursor and to bond the conductive particles together.
    Type: Application
    Filed: March 2, 2004
    Publication date: December 2, 2004
    Inventors: Tetsuya Otsuki, Hirofumi Kurosawa, Hiroshi Miki
  • Publication number: 20040237296
    Abstract: A receiving layer formed of a thermoplastic resin is softened by applying heat. By using a solvent containing conductive particles, an interconnect layer is formed on the receiving layer which is softened by the application of heat. The conductive particles are bonded together by heating the interconnect layer.
    Type: Application
    Filed: March 2, 2004
    Publication date: December 2, 2004
    Inventors: Tetsuya Otsuki, Hirofumi Kurosawa, Hiroshi Miki
  • Patent number: 6822276
    Abstract: It is an object of the present invention to provide a fine memory cell structure preventing a reaction between an interlayer insulating film and a ferroelectric film and suitable for high integration. According to the invention, there is provided a structure in which a reaction barrier film 43 is interposed between a ferroelectric film 71 and an interlayer insulating film 32 and side walls of a diffusion barrier film 51 are not brought into direct contact with the ferroelectric film 71. Thereby, the reaction between the interlayer insulating film 32 and the ferroelectric film 71 can be restrained and exfoliation of the ferroelectric film 71 can be prevented.
    Type: Grant
    Filed: September 7, 1999
    Date of Patent: November 23, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Kazuyoshi Torii, Hiroshi Miki, Yoshihisa Fujisaki
  • Patent number: 6818523
    Abstract: A method for forming a semiconductor storage device includes steps of forming a memory cell transistor, forming a first plug connected to the memory cell transistor, forming a second plug of a hydrogen diffusion inhibiting layer, forming capacitor electrodes and a capacitor insulator between the capacitor electrodes and forming a hydrogen adsorption inhibiting layer.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: November 16, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Miki, Keiko Kushida, Yasuhiro Shimamoto, Shinichiro Takatani, Yoshihisa Fujisaki, Hiromi Nakai
  • Patent number: 6800889
    Abstract: A semiconductor device includes a capacitor having a lower electrode (102), a high-dielectric-constant or ferroelectric thin film (103), and an upper electrode (104) which are subsequently stacked. An impurity having an action of suppressing the catalytic activity of a metal or a conductive oxide constituting the electrode is added to the upper electrode (104). The addition of the impurity is effective to prevent inconveniences such as a reduction in capacitance, an insulation failure, and the peeling of the electrode due to hydrogen heat-treatment performed after formation of the upper electrode (104), and to improve the long-term reliability.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: October 5, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Shinichiro Takatani, Hiroshi Miki, Keiko Kushida, Yoshihisa Fujisaki, Kazuyoshi Torii
  • Patent number: 6740901
    Abstract: A semiconductor integrated circuit in which the storage capacitor has an increased capacitance and a decreased leakage current. The storage capacitor is formed by the steps of: forming a polysilicon bottom electrode having semispherical silicon crystals formed thereon; performing plasma nitriding on the surface of said bottom electrode at a temperature lower than 550° C., thereby forming a film of silicon nitride having a film thickness smaller than 1.5 nm; and depositing a film of amorphous tantalum pentoxide and then crystallizing said amorphous tantalum pentoxide. The silicon nitride film has improved resistance to oxidation and also has a reduced leakage current. As a result, the polysilicon bottom electrode becomes resistant to oxidation and the storage capacitor increases in capacitance and decreases in leakage current.
    Type: Grant
    Filed: December 2, 2002
    Date of Patent: May 25, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Hiroshi Miki, Yasuhiro Shimamoto, Masahiko Hiratani, Tomoyuki Hamada
  • Publication number: 20040063280
    Abstract: The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively acts as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.
    Type: Application
    Filed: June 25, 2003
    Publication date: April 1, 2004
    Inventors: Hiroshi Miki, Keiko Kushida, Yasuhiro Shimamoto, Shinichiro Takatani, Yoshihisa Fujisaki, Hiromi Nakai
  • Patent number: 6693792
    Abstract: A capacitor having an equivalent thickness of 3.0 nm or less, with a sufficient static capacitance and less leakage current in a reduced size, constituted by stacking an interfacial film 21 having a physical thickness of 2.5 nm or more for suppressing tunnel leakage current and a high dielectric film 22 comprising tantalum pentaoxide on lower electrode 19, 20 comprising rugged polycrystal silicon film, the interfacial film 21 comprising a nitride film formed by an LPCVD method, for example, from Al2O3, a mixed phase of Al2O3 and SiO2, ZrSiO4, HfSiO4, a mixed phase of Y2O3 and SiO2, and a mixed phase of La2O3 and SiO2.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: February 17, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yasuhiro Shimamoto, Hiroshi Miki, Masahiko Hiratani
  • Publication number: 20030205752
    Abstract: A capacitor having an equivalent thickness of 3.0 nm or less, with a sufficient static capacitance and less leakage current in a reduced size, constituted by stacking an interfacial film 21 having a physical thickness of 2.5 nm or more for suppressing tunnel leakage current and a high dielectric film 22 comprising tantalum pentaoxide on lower electrode 19, 20 comprising rugged polycrystal silicon film, the interfacial film 21 comprising a nitride film formed by an LPCVD method, for example, from Al2O3, a mixed phase of Al2O3 and SiO2, ZrSiO4, HfSiO4, a mixed phase of Y2O3 and SiO2, and a mixed phase of La2O3 and SiO2.
    Type: Application
    Filed: April 11, 2003
    Publication date: November 6, 2003
    Inventors: Yasuhiro Shimamoto, Hiroshi Miki, Masahiko Hiratani
  • Patent number: 6635913
    Abstract: The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively act as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: October 21, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Miki, Keiko Kushida, Yasuhiro Shimamoto, Shinichiro Takatani, Yoshihisa Fujisaki, Hiromi Nakai