Patents by Inventor Hiroshi Mochizuki

Hiroshi Mochizuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5548151
    Abstract: In a Hall element, a semiconductor layer is surrounded by a first trench filled with an insulator. A first current supply portion of an n+-type semiconductor is disposed adjacent the semiconductor layer and the first trench. Second current supply portions are also disposed adjacent the semiconductor layer and the first trench and symmetrical with respect to the first current supply portion. Sensor portions of an n+-type semiconductor are disposed adjacent the semiconductor layer and the first trench at about the center between the first and second current supply portions, respectively. A magnetic flux perpendicular to the upper surface of the semiconductor layer can be detected by the foregoing arrangement.
    Type: Grant
    Filed: February 7, 1995
    Date of Patent: August 20, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Funaki, Hiroshi Mochizuki, Ryoji Maruyama, Kanae Fujii
  • Patent number: 5438139
    Abstract: Acridinium compounds represented by the general formula (I) where A is an intervening group which does not have activity for binding with a specific binding substance, Z is a labelling active group which has activity for binding with a specific binding substance, R.sup.1 is a halogen atom, an alkyl group or an aryl group; R.sup.2, R.sup.3, R.sup.4 and R.sup.5 are each a hydrogen atom, an alkyl group, an aryl group, an alkoxy group, a nitro group, a halogen atom or a carbonyl group, and Y is a counter ion. The acridinium compounds may form conjugates with specific binding substances. The acridinium compounds have high emission efficiency and stability and, hence, are useful as chemiluminescence labelling agents.
    Type: Grant
    Filed: January 31, 1994
    Date of Patent: August 1, 1995
    Assignee: Mochida Pharmaceutical Co., Ltd.
    Inventors: Naofumi Sato, Hiroshi Mochizuki, Toshinori Kanamori
  • Patent number: 5306947
    Abstract: The present invention is mainly characterized by providing an even surface of an interlayer insulating film for insulating and isolating an upper interconnection and a lower interconnection from each other. A lower interconnection layer is provided on a semiconductor substrate, having a pattern of stepped portions. A silicon type insulating film is provided on the semiconductor substrate so as to cover the lower interconnection layer. A silicon ladder resin film is filled in recessed portions of the surface of the silicon type insulating film for making even the surface of the silicon type insulating film. An upper interconnection layer electrically connected to the lower interconnection layer through a via hole is provided on the silicon type insulating film. The silicon ladder resin film has the structural formula: ##STR1## where R.sub.1 is at least one of a phenyl group and a lower alkyl group, R.sub.2 is at least one of a hydrogen atom and a lower alkyl group, and n is an integer of 20 to 1000.
    Type: Grant
    Filed: January 13, 1993
    Date of Patent: April 26, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroshi Adachi, Hirozoh Kanegae, Hiroshi Mochizuki, Masanori Obata, Takemi Endoh, Kimio Hagi, Shigeru Harada, Kazuhito Matsukawa, Akira Ohhisa, Etsushi Adachi
  • Patent number: 5278451
    Abstract: A semiconductor device sealed with mold resin is disclosed. The device includes a semiconductor substrate having a main surface and an element formed on the main surface of the semiconductor substrate. A stress buffering film for protecting at least the element from stress of the mold resin is provided on the semiconductor substrate so as to cover at least the element. The entire semiconductor device is covered and sealed with mold resin. The stress buffering film is formed of organo-silicone ladder polymer having a hydroxyl group at its end. In the semiconductor device, water does not get into an interface of the stress buffering film and the underlying substrate, resulting in an enhancement of the moisture resistance of the semiconductor device.
    Type: Grant
    Filed: September 30, 1991
    Date of Patent: January 11, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Etsushi Adachi, Hiroshi Adachi, Hiroshi Mochizuki
  • Patent number: 5262526
    Abstract: A fluorescent compound, which is readily capable of forming a stable complex with a rare-earth metal ion having fluorescence with satisfactory intensity even in an aqueous system and long fluorescence lifetime when formed a complex with the rare-earth metal ion, a complex of the fluorescent compound and the rare-earth metal ion, and a labelled reagent made therefrom, together with a specific binding assay using said labelling agent.A fluorescent compound expressed by the following formula A, typically exemplified by 2,15-diaza[3,3](2,9)-1,10-phenanthrolinophane-N.sup.2,N.sup.15 -diacetic acid.
    Type: Grant
    Filed: December 20, 1991
    Date of Patent: November 16, 1993
    Assignees: Dojindo Laboratories, Mochida Pharmaceutical Co., Ltd.
    Inventors: Kazumi Sasamoto, Daikichi Horiguchi, Masahiro Nobuhara, Hiroshi Mochizuki
  • Patent number: 5243538
    Abstract: When a hierarchy design is attempted in a logic design of a logic circuit, a system for verifying an equivalence between an upper level logic and a lower level logic is required. When the two different level logics are compared, the logics are once converted to Boolean expressions regardless of logic expressions of the logics, involving a logic circuit diagram and a truth table, and Shannon's formula is applied to the two Boolean expressions under a same order of variables to be extracted, to thereby produce binary decision diagrams (BDDs). When the equivalence between the produced BDDs is determined, the BDDs are simplified, respectively, and the simplified BDDs are integrated from the branches, and a determination can be carried out one time, i.e, without a repeat process.
    Type: Grant
    Filed: August 7, 1990
    Date of Patent: September 7, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Osamu Okuzawa, Kazuhiko Matsumoto, Yukio Ikariya, Hiroshi Mochizuki
  • Patent number: 5198880
    Abstract: For providing a semiconductor integrated circuit device including CCD type, bipolar type and MOS type integrated circuits in only one chip, island-shaped epitaxial layers of opposite conductivity type are disposed in a semiconductor substrate of one conductivity type having a low impurity concentration. A field oxide layer is provided so as to surround a periphery of an exposed surface of each epitaxial layer. A buried layer of opposite conductivity type having a high impurity concentration is is interposed between the semiconductor substrate and each epitaxial layer in such a manner that at least one edge thereof terminates to the lower surfaace of the field oxide layer. The CCD type integrated circuit is provided in the semiconductor substrate, and the bipolar type and MOS type integrated circuits are arranged in the epitaxial layers.
    Type: Grant
    Filed: October 28, 1991
    Date of Patent: March 30, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Minoru Taguchi, Hiroshi Mochizuki
  • Patent number: 5181197
    Abstract: An optical disk driver using a top-loading mechanism is coupled to an operational processor, such as a personal computer. The term "a top-loading mechanism" means a mechanism for inserting and/or ejecting an optical disk via a top surface of the optical disk driver. Additionally, a display unit used for the operational processor can be located on an operational processing apparatus comprising such an optical disk driver and an operational processor.
    Type: Grant
    Filed: January 28, 1991
    Date of Patent: January 19, 1993
    Assignee: Mitsumi Electric Co., Ltd.
    Inventors: Noboru Sugie, Kenichi Furukawa, Makoto Ogawa, Hironori Kurisu, Tomonori Mitsui, Akio Aito, Mitsunori Nakamura, Hiroshi Mochizuki
  • Patent number: 5180691
    Abstract: The disclosed is a method of manufacturing a semiconductor device sealed with molding resin. An aluminum interconnection including an aluminum electrode pad is formed on a semiconductor substrate having an element. A silicone ladder polymer expressed by the following general formula is formed on the semiconductor substrate to cover the element. The silicone ladder polymer film is selectively etched by an aromatic organic solvent to expose the surface of the aluminum electrode pad. The temperature of the silicone ladder polymer film is elevated at a temperature elevating rate of 20.degree. C./min or more, and then, the silicone ladder polymer film is cooled at a cooling rate of 20.degree. C./min or more to form a cured stress buffering protective film for buffering a stress applied to the element. ##STR1## (in the formula, n is an integer which makes the weight-average molecular weight be in the range of 100,000 to 200,000.
    Type: Grant
    Filed: January 30, 1992
    Date of Patent: January 19, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Etsushi Adachi, Hiroshi Adachi, Hiroshi Mochizuki, Hirozoh Kanegae
  • Patent number: 5115777
    Abstract: A method and an apparatus for driving an auxiliary device of an internal combustion engine according to the present invention is directed to preventing an over revolution of an engine by detecting a speed of the revolution of the engine, regardless the magnitude of an induced voltage of a primary winding of an ignition device.
    Type: Grant
    Filed: February 22, 1990
    Date of Patent: May 26, 1992
    Assignee: Iida Denki Kogyo Co., Ltd.
    Inventors: Yoshinori Ohki, Hiroshi Mochizuki
  • Patent number: 4884120
    Abstract: An improved interconnection structure and method for forming the interconnection in a semiconductor device having multilayered interconnection structure in which a contact hole for electrically connecting a first layer interconnection to a predetermined region of a semiconductor substrate and a through hole for electrically connecting a second layer interconnection to the first layer interconnection are formed in the regions overlapping with each other in planer layout. In the interconnection structure of the present invention, hillocks effective to compensate for the contact hole step are formed in the first layer interconnection only in the region of the contact hole of the first layer interconnection.
    Type: Grant
    Filed: February 20, 1987
    Date of Patent: November 28, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroshi Mochizuki, Reiji Tamaki, Junichi Arima, Masaaki Ikegami, Eisuke Tanaka, Kenji Saito
  • Patent number: 4867859
    Abstract: An apparatus for forming a thin film on a substrate has a first reaction chamber in which a thin film is formed by gaseous discharge and a second reaction chamber in which reactive atoms are generated. The first and second reaction chambers commuicate with one another through an orifice in the first reaction chamber. The first reaction chamber houses a device for generating a film on a substrate, and the second reaction chamber houses a device for generating reactive atoms. The orifice is disposed in the vicinity of both a film-forming region in the first reaction chamber and a reactive atom-generating region in the second reaction chamber so that reactive atoms from the second reaction chamber will pass through the orifice and enter the film-forming region in the first reaction chamber, combine with particles in the film-forming region to form a chemical compound, and accumulate on the substrate.
    Type: Grant
    Filed: August 4, 1987
    Date of Patent: September 19, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shigeru Harada, Takeshi Noguchi, Hiroshi Mochizuki
  • Patent number: 4752915
    Abstract: A memory apparatus is managed by two-dimensional addresses consisting of X and Y addresses and is divided into a plurality of memory banks. One of the memory banks is selected by lower significant bits including the least significant bit in each of the X and Y addresses. A different memory bank is selected by the updating of the X address or by the updating of the Y address.
    Type: Grant
    Filed: August 16, 1985
    Date of Patent: June 21, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Kenji Suzuki, Hiroshi Mochizuki
  • Patent number: 4388953
    Abstract: Apparatus for twisting a wire end comprises a wire holder, a twisting means for selectively engaging the wire end, a drive means operable to rotate the twisting means, and an actuator means operable to move one of the wire holder and the twisting means toward the other to allow the twisting means to engage the wire end. The actuator means is operable to move the one away from the other while the drive means rotates the twisting means, thereby twisting the wire end about its axis.
    Type: Grant
    Filed: January 5, 1981
    Date of Patent: June 21, 1983
    Assignee: Osawa Press Mdg., Co., Ltd.
    Inventors: Akinori Hara, Hiroshi Mochizuki
  • Patent number: 4295414
    Abstract: A diaphragm-type fuel pump defining therein an outlet chamber for supplying fuel to a carburetor. A return pipe is connected to the interior of the outlet chamber to permit return of vapors to the fuel tank. An outlet pipe communicates with the outlet chamber for supplying fuel to the carburetor float chamber. The fuel pump has an outlet valve associated therewith for supplying fuel into the outlet chamber. The open inlet end of the return pipe communicates with the outlet chamber at an elevation which is higher than the elevation of the outlet valve, and the inlet opening of the outlet pipe communicates with the outlet chamber at an elevation which is lower than the elevation of the outlet valve, whereby vapors within the outlet chamber are prevented from passing through the outlet pipe to the carburetor.
    Type: Grant
    Filed: August 9, 1979
    Date of Patent: October 20, 1981
    Assignee: Kyosan Denki Kabushiki Kaisha
    Inventors: Hiroshi Mochizuki, Tokio Seki
  • Patent number: D320858
    Type: Grant
    Filed: March 14, 1989
    Date of Patent: October 15, 1991
    Assignee: Terumo Kabushiki Kaisha
    Inventors: Kenichi Kida, Hiroshi Mochizuki
  • Patent number: D324425
    Type: Grant
    Filed: December 8, 1989
    Date of Patent: March 3, 1992
    Assignee: Terumo Kabushiki Kaisha
    Inventors: Masashi Yoshikawa, Hiroshi Mochizuki
  • Patent number: D327324
    Type: Grant
    Filed: March 26, 1990
    Date of Patent: June 23, 1992
    Assignee: Terumo Kabushiki Kaisha
    Inventors: Tetsuya Arioka, Hiroshi Mochizuki
  • Patent number: D345607
    Type: Grant
    Filed: December 21, 1992
    Date of Patent: March 29, 1994
    Assignee: Terumo Kabushiki Kaisha
    Inventors: Atsushi Sodeoka, Hiroshi Mochizuki
  • Patent number: D356377
    Type: Grant
    Filed: January 10, 1994
    Date of Patent: March 14, 1995
    Assignee: Terumo Kabushiki Kaisha
    Inventors: Jun Tsubota, Hiroshi Mochizuki