Patents by Inventor Hiroshi Seki
Hiroshi Seki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7969897Abstract: A relay device for relaying transfer data to be transmitted between the devices has a plurality of testers. Each of the testers determines whether received transfer data is normal or not, and discards the transfer data that is determined abnormal. The relay device also has a counter that counts a number of transfer data discarded by each of the testers respectively, and a determiner that determines whether an operation of each tester is normal or not based on the number of discarded transfer data counted by the counter.Type: GrantFiled: November 26, 2008Date of Patent: June 28, 2011Assignee: Fujitsu LimitedInventors: Hiroshi Seki, Hiroyuki Kaneda, Masayuki Kanno, Akira Nakamizu, Syuuhei Ueno
-
Publication number: 20110074551Abstract: A radio-type transmitting device capable of transmitting information other than information in an internal memory is provided. A RFID tag includes a encoding circuit for digitalizing receiving sensitivity of a radio wave sent from an external transmitting/receiving apparatus and then sending the digitalized receiving sensitivity to the external transmitting/receiving apparatus. Thus, the external transmitting/receiving apparatus can obtain a distance between the external transmitting/receiving apparatus and the RFID tag based on received sensitivity information.Type: ApplicationFiled: September 24, 2010Publication date: March 31, 2011Applicant: Panasonic CorporationInventors: Masaru HIGASHIONJI, Kenji Hasegawa, Masaru Odagiri, Masafumi Shimotashiro, Hiroshi Seki
-
Publication number: 20100308874Abstract: A clock switch circuit includes a frequency divide circuit which divides a frequency of a basic clock to generate a plurality of frequency-divided clocks, an output select signal generation circuit which outputs an output select signal according to a clock select signal, and an output select circuit which switches a clock to be output according to the output select signal, in which the frequency divide circuit outputs a plurality of frequency-divided count values indicating the number of clocks of the basic clock from start of one cycle of each of the frequency-divided clocks, and the output select signal generation circuit switches a value of the output select signal at timings at which start timings of cycles of frequency-divided clocks before and after switch operation are matched based on a frequency-divided count value corresponding to a current selection clock among the plurality of frequency-divided count values.Type: ApplicationFiled: May 26, 2010Publication date: December 9, 2010Applicant: NEC Electronics CorporationInventors: Hiroshi SEKI, Kiyoshi Kirino
-
Patent number: 7821410Abstract: A radio-type transmitting device capable of transmitting information other than information in an internal memory is provided. A RFID tag includes a encoding circuit for digitalizing receiving sensitivity of a radio wave sent from an external transmitting/receiving apparatus and then sending the digitalized receiving sensitivity to the external transmitting/receiving apparatus. Thus, the external transmitting/receiving apparatus can obtain a distance between the external transmitting/receiving apparatus and the RFID tag based on received sensitivity information.Type: GrantFiled: July 3, 2006Date of Patent: October 26, 2010Assignee: Panasonic CorporationInventors: Masaru Higashionji, Kenji Hasegawa, Masaru Odagiri, Masafumi Shimotashiro, Hiroshi Seki
-
Patent number: 7656210Abstract: A semiconductor integrated circuit that operates on multiple supply potentials including a first potential and a second potential that is higher than the first potential. The semiconductor integrated circuit includes a potential-lowering circuit operating on the second supply potential and including an N-channel MOS transistor that lowers the second supply potential applied to a gate thereof to output a lowered potential from a source thereof, a judging circuit operating on the potential outputted from the potential-lowering circuit and judging whether the first supply potential is high-level or low-level, and a buffer circuit outputting a control signal showing whether the first supply potential is fed based on judgment outputted from the judging circuit.Type: GrantFiled: April 13, 2006Date of Patent: February 2, 2010Assignee: Seiko Epson CorporationInventors: Hiroshi Seki, Hideyuki Kakubari, Hiroshi Tokiwai
-
Patent number: 7577022Abstract: An electric element includes: a first electrode (1); a second electrode (3); and a layer (2) connected between the first electrode and the second electrode and having a diode characteristic and a variable resistance characteristic. The layer (2) conducts a substantial electric current in a forward direction extending from one of the first electrode (1) and the second electrode (3) to the other electrode as compared to a reverse direction opposite of the forward direction. The resistance value of the layer (2) for the forward direction increases or decreases according to a predetermined pulse voltage applied between the first electrode (1) and the second electrode (3).Type: GrantFiled: September 9, 2005Date of Patent: August 18, 2009Assignee: Panasonic CorporationInventors: Shunsaku Muraoka, Koichi Osano, Satoru Mitani, Hiroshi Seki
-
Publication number: 20090189660Abstract: A semiconductor device includes an input circuit, an output circuit, and a test circuit that is adapted to evaluate delaying of a signal which is input to the input circuit to be output from the output circuit.Type: ApplicationFiled: January 28, 2009Publication date: July 30, 2009Applicant: SEIKO EPSON CORPORATIONInventor: Hiroshi SEKI
-
Patent number: 7567111Abstract: A semiconductor integrated circuit operates at two or more supply potentials including a first supply potential and a second supply potential that is higher than the first supply potential, and includes (1) an internal circuit that operates at the first supply potential, (2) an inverter that inverts a control signal fed from the internal circuit and outputs the inverted control signal, when the first supply potential is fed, (3) a level-shifting circuit that inputs the control signal to a first input terminal, while inputting the inverted control signal to a second input terminal, and outputs, from an output terminal, a level-shifted signal of the signal inputted to the first or the second terminal, when the second supply potential is fed, (4) a first input circuit that performs a logical operation on the basis of an input signal inputted via an input pad and a level-shifted signal outputted from the level-shifting circuit, when the second supply potential is fed, thereby outputting a signal corresponding toType: GrantFiled: June 13, 2006Date of Patent: July 28, 2009Assignee: Seiko Epson CorporationInventors: Hiroshi Seki, Hiroshi Tokiwai
-
Patent number: 7564288Abstract: A semiconductor integrated circuit that operates upon supply of a plurality of power potentials including a first power potential and a second power potential higher than the first power potential, includes: an internal circuit that operates upon supply of the first power potential; an inverter that inverts an output signal of the internal circuit upon supply of the first power potential; a level shift circuit, which inputs the output signal of the internal circuit into a first input terminal while inputting the output signal of the inverter into a second input terminal, which generates, upon supply of the second power potential and at each of first and second output terminals, a level shift signal input into the first and second input terminals whose signal level has been shifted, and which outputs the level shift signal from one terminal out of the first and second output terminals; an output circuit that operates upon supply of the second power potential based on the level shift signal output from the leveType: GrantFiled: June 12, 2006Date of Patent: July 21, 2009Assignee: Seiko Epson CorporationInventors: Hiroshi Seki, Hiroshi Tokiwai
-
Publication number: 20090147691Abstract: A relay device for relaying transfer data to be transmitted between the devices has a plurality of testers. Each of the testers determines whether received transfer data is normal or not, and discards the transfer data that is determined abnormal. The relay device also has a counter that counts a number of transfer data discarded by each of the testers respectively, and a determiner that determines whether an operation of each tester is normal or not based on the number of discarded transfer data counted by the counter.Type: ApplicationFiled: November 26, 2008Publication date: June 11, 2009Applicant: FUJITSU LIMITEDInventors: Hiroshi SEKI, Hiroyuki Kaneda, Masayuki Kanno, Akira Nakamizu, Syuuhei Ueno
-
Patent number: 7525832Abstract: First electrode layer includes a plurality of first electrode lines (W1, W2) extending parallel to each other. State-variable layer lying on the first electrode layer includes a plurality of state-variable portions (60-11, 60-12, 60-21, 60-22) which exhibits a diode characteristic and a variable-resistance characteristic. Second electrode layer lying on the state-variable layer includes a plurality of second electrode lines (B1, B2) extending parallel to each other. The plurality of first electrode lines and the plurality of second electrode lines are crossing each other when seen in a layer-stacking direction with the state-variable layer interposed therebetween. State-variable portion (60-11) is provided at an intersection of the first electrode line (W1) and the second electrode line (B1) between the first electrode line and the second electrode line.Type: GrantFiled: April 21, 2006Date of Patent: April 28, 2009Assignee: Panasonic CorporationInventors: Shunsaku Muraoka, Koichi Osano, Satoru Mitani, Hiroshi Seki
-
Publication number: 20090067215Abstract: An electric element comprises: a first electrode (1); a second electrode (3); and a layer (2) connected between the first electrode and the second electrode and having a diode characteristic and a variable resistance characteristic. The layer (2) conducts a substantial electric current in a forward direction extending from one of the first electrode (1) and the second electrode (3) to the other electrode as compared to a reverse direction opposite of the forward direction. The resistance value of the layer (2) for the forward direction increases or decreases according to a predetermined pulse voltage applied between the first electrode (1) and the second electrode (3).Type: ApplicationFiled: September 9, 2005Publication date: March 12, 2009Inventors: Shunsaku Muraoka, Koichi Osano, Satoru Mitani, Hiroshi Seki
-
Publication number: 20080212359Abstract: First electrode layer includes a plurality of first electrode lines (W1, W2) extending parallel to each other. State-variable layer lying on the first electrode layer includes a plurality of state-variable portions (60-11, 60-12, 60-21, 60-22) which exhibits a diode characteristic and a variable-resistance characteristic. Second electrode layer lying on the state-variable layer includes a plurality of second electrode lines (B1, B2) extending parallel to each other. The plurality of first electrode lines and the plurality of second electrode lines are crossing each other when seen in a layer-stacking direction with the state-variable layer interposed therebetween. State-variable portion (60-11) is provided at an intersection of the first electrode line (W1) and the second electrode line (B1) between the first electrode line and the second electrode line.Type: ApplicationFiled: April 21, 2006Publication date: September 4, 2008Inventors: Shunsaku Muraoka, Koichi Osano, Satoru Mitani, Hiroshi Seki
-
Patent number: 7350855Abstract: A water drainage structure is provided to prevent drainage water from getting on hot components inside the engine compartment and suppress the occurrence of evaporation noise. At least one water drainage opening is provided in a bottom portion of a vehicle member arranged on the under surface of a floor panel of a vehicle. The downstream end portion of a water drainage pipe is arranged to communicate with the inside of a closed cross sectional structure formed by the floor panel and the vehicle member. Drainage water from a vehicle device flows out of the downstream end portion of the water drainage pipe and is discharged to the outside of the vehicle through the water drainage openings of the vehicle member. As a result, the drainage water is prevented from getting on hot components inside the engine compartment of the vehicle and the occurrence of evaporation noise is suppressed.Type: GrantFiled: July 5, 2006Date of Patent: April 1, 2008Assignee: Nissan Motor Co., Ltd.Inventor: Hiroshi Seki
-
Patent number: 7191421Abstract: An integrated circuit design apparatus includes a block placement processing unit which performs processing of creation of a lower-rank mounting block in a higher-rank mounting block, and performs processing of creation of virtual placement regions in each of the lower-rank mounting block and the higher-rank mounting block. A functional block assignment processing unit performs processing of assignment of functional blocks to each of the virtual placement regions provided by the block placement processing unit. An evaluation processing unit provides a display of a condition of the functional blocks assigned to each of the virtual placement regions of both the lower-rank mounting block and the higher-rank mounting block, in order to evaluate the condition of the assigned functional blocks.Type: GrantFiled: March 25, 2002Date of Patent: March 13, 2007Assignee: Fujitsu LimitedInventors: Yasuo Amano, Hiroshi Seki, Yukio Makino, Yumiko Yamanishi, Yoshiko Nakanishi, Yoichiro Ishikawa
-
Publication number: 20070018833Abstract: A radio-type transmitting device capable of transmitting information other than information in an internal memory is provided. A RFID tag includes a encoding circuit for digitalizing receiving sensitivity of a radio wave sent from an external transmitting/receiving apparatus and then sending the digitalized receiving sensitivity to the external transmitting/receiving apparatus. Thus, the external transmitting/receiving apparatus can obtain a distance between the external transmitting/receiving apparatus and the RFID tag based on received sensitivity information.Type: ApplicationFiled: July 3, 2006Publication date: January 25, 2007Inventors: Masaru Higashionji, Kenji Hasegawa, Masaru Odagiri, Masafumi Shimotashiro, Hiroshi Seki
-
Publication number: 20070007797Abstract: A water drainage structure is provided to prevent drainage water from getting on hot components inside the engine compartment and suppress the occurrence of evaporation noise. At least one water drainage opening is provided in a bottom portion of a vehicle member arranged on the under surface of a floor panel of a vehicle. The downstream end portion of a water drainage pipe is arranged to communicate with the inside of a closed cross sectional structure formed by the floor panel and the vehicle member. Drainage water from a vehicle device flows out of the downstream end portion of the water drainage pipe and is discharged to the outside of the vehicle through the water drainage openings of the vehicle member. As a result, the drainage water is prevented from getting on hot components inside the engine compartment of the vehicle and the occurrence of evaporation noise is suppressed.Type: ApplicationFiled: July 5, 2006Publication date: January 11, 2007Applicant: Nissan Motor Co., LtdInventor: Hiroshi Seki
-
Patent number: 7154350Abstract: The invention provides technologies which can restrict damage due to static electricity to a gate insulating film of a transistor inside a semiconductor device forming an oscillating circuit. In particular, an oscillating circuit can include an oscillator and a semiconductor device which utilizes the oscillator. The semiconductor device can include an inverting amplifier which is provided in parallel with the oscillator and comprises an insulated gate type field effect transistor; a buffer circuit which includes an insulated gate type field effect transistor and is used to send out a signal output from the inverting amplifier to another circuit, and a transmission gate which is provided between the output terminal of the inverting amplifier and the input terminal of the buffer circuit, and includes an insulated gate type field effect transistor.Type: GrantFiled: September 9, 2003Date of Patent: December 26, 2006Assignee: Seiko Epson CorporationInventor: Hiroshi Seki
-
Publication number: 20060279347Abstract: A semiconductor integrated circuit operates at two or more supply potentials including a first supply potential and a second supply potential that is higher than the first supply potential, and includes (1) an internal circuit that operates at the first supply potential, (2) an inverter that inverts a control signal fed from the internal circuit and outputs the inverted control signal, when the first supply potential is fed, (3) a level-shifting circuit that inputs the control signal to a first input terminal, while inputting the inverted control signal to a second input terminal, and outputs, from an output terminal, a level-shifted signal of the signal inputted to the first or the second terminal, when the second supply potential is fed, (4) a first input circuit that performs a logical operation on the basis of an input signal inputted via an input pad and a level-shifted signal outputted from the level-shifting circuit, when the second supply potential is fed, thereby outputting a signal corresponding toType: ApplicationFiled: June 13, 2006Publication date: December 14, 2006Applicant: SEIKO EPSON CORPORATIONInventors: Hiroshi SEKI, Hiroshi TOKIWAI
-
Publication number: 20060279346Abstract: A semiconductor integrated circuit that operates upon supply of a plurality of power potentials including a first power potential and a second power potential higher than the first power potential, includes: an internal circuit that operates upon supply of the first power potential; an inverter that inverts an output signal of the internal circuit upon supply of the first power potential; a level shift circuit, which inputs the output signal of the internal circuit into a first input terminal while inputting the output signal of the inverter into a second input terminal, which generates, upon supply of the second power potential and at each of first and second output terminals, a level shift signal input into the first and second input terminals whose signal level has been shifted, and which outputs the level shift signal from one terminal out of the first and second output terminals; an output circuit that operates upon supply of the second power potential based on the level shift signal output from the leveType: ApplicationFiled: June 12, 2006Publication date: December 14, 2006Applicant: SEIKO EPSON CORPORATIONInventors: Hiroshi SEKI, Hiroshi TOKIWAI