Patents by Inventor Hiroshi Shinriki

Hiroshi Shinriki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040005408
    Abstract: A method of forming a dielectric film on a Si substrate comprises the steps of adsorbing a gaseous molecular compound of a metal element constituting a dielectric material on a Si substrate, and causing a decomposition of the gaseous molecular compound thus adsorbed by a hydrolysis process or pyrolytic decomposition process or an oxidation process.
    Type: Application
    Filed: December 6, 2002
    Publication date: January 8, 2004
    Inventors: Hideki Kiryu, Shintaro Aoyama, Tsuyoshi Takahashi, Hiroshi Shinriki
  • Publication number: 20030236001
    Abstract: A method of fabrication a semiconductor device includes the steps of forming an insulation film containing Si and oxygen on a silicon substrate, and depositing a metal oxide film on the insulation film by a chemical vapor deposition process that uses a metal organic source material, wherein the step of depositing the metal oxide film is conducted such that the metal oxide film takes a crystalline state immediately after the deposition step.
    Type: Application
    Filed: June 10, 2003
    Publication date: December 25, 2003
    Applicant: Tokyo Electron Limited
    Inventors: Hiroshi Shinriki, Kazumi Kubo
  • Publication number: 20030170945
    Abstract: A method of nitriding an insulation film, includes the steps of forming nitrogen radicals by high-frequency plasma, and causing nitridation in a surface of an insulation film containing therein oxygen, by supplying the nitrogen radicals to the surface of the insulation film.
    Type: Application
    Filed: December 6, 2002
    Publication date: September 11, 2003
    Applicant: Tokyo Electron Limited
    Inventors: Masanobu Igeta, Shintaro Aoyama, Hiroshi Shinriki, Tsuyoshi Takahashi
  • Publication number: 20030170388
    Abstract: A shower head 9 having a plurality of ejection holes for supplying an organic metal gas at uniform density to the surface of a substrate 10 and a plurality of ejection holes for supplying an oxidizing gas at uniform density to the same is provided in a reaction furnace 8 of an MOSVD system. A heater for heating the inside to a temperature higher than the thermal decomposition point of the organic metal gas but lower than the film forming temperature is provided in the vicinity of the substrate-side surface of the shower head 9.
    Type: Application
    Filed: March 12, 2003
    Publication date: September 11, 2003
    Inventors: Hiroshi Shinriki, Kenji Matsumoto, Toru Tatsumi
  • Patent number: 6485564
    Abstract: In a thin film forming method of the invention, an atmosphere for a base as a thin film forming target is set to a high vacuum of, e.g., 0.01 Torr or less, and a gas of an organometallic compound and an oxidizing gas are introduced onto a base surface heated to about 450° C., to form a plurality of crystal nuclei, made of an oxide of a metal constituting the organometallic compound, on the base surface. The atmosphere for the base is then set to a lower vacuum than the first vacuum degree, and the gas of the organometallic compound and the oxidizing gas are subsequently introduced onto the base surface heated to about 45° C., to form a film made of the oxide of the metal there.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: November 26, 2002
    Assignee: Tokyo Electron Limited
    Inventors: Yijun Liu, Hiroshi Shinriki, Takashi Magara
  • Patent number: 6482266
    Abstract: In a metal organic chemical vapor deposition method, a parameter convertible into the number of moles of gas of an organometallic source supplied from at least one source vessel is detected. A source contained in the source vessel is heated when the parameter becomes smaller than a minimum value necessary for forming a thin film of a metal constituting the organometallic source on a substrate in a reactor. The gas of the organometallic source is quantitatively supplied to the reactor, thereby forming the thin film on the substrate. A metal organic chemical vapor deposition apparatus is also disclosed.
    Type: Grant
    Filed: June 21, 2000
    Date of Patent: November 19, 2002
    Assignee: Tokyo Electron Limted
    Inventors: Kenji Matsumoto, Hiroshi Shinriki
  • Publication number: 20020166507
    Abstract: The vacuum degree in a reactor is set to as low as 0.1 Torr. In this state, a butyl acetate solution in which Pb(DPM)2 is dissolved at a concentration of 0.1 mol is transported from a Pb source generator to an evaporator, while the flow rate of the butyl acetate solution is controlled to a predetermined flow rate by a massflow controller, to evaporate the Pb(DPM)2 dissolved together with the butyl acetate by the evaporator. Helium gas is added to these at a flow rate of 250 sccm, and the mixed gas is transported to a shower head. With this operation, source gases are supplied to a wafer in the reactor, while the partial pressure of each source gas is set low.
    Type: Application
    Filed: April 29, 2002
    Publication date: November 14, 2002
    Applicant: Tokyo Electron Limited
    Inventors: Hiroshi Shinriki, Kenji Matsumoto
  • Patent number: 6467491
    Abstract: A pretreatment chamber 120 is disposed within a vacuum transfer chamber 102 of a processing apparatus 100. The pretreatment chamber 120 is equipped with an orienting mechanism 128 and a UV lamp 124. The orienting mechanism 128 orients a wafer W through rotation of a table 130, on which the wafer W is placed, and by use of an optical sensor 134. Synchronously with the orientation, the UV lamp 124 emits UV through a UV transmission window 126 fitted to a ceiling portion of the pretreatment chamber 120, to thereby irradiate the surface of the wafer W with UV. Thus adhering to the wafer W is removed. A processing gas supplied into the pretreatment chamber 120 is also irradiated with UV. Active atoms generated from the processing gas also contribute to removal of carbon. Since the pretreatment chamber 120 is formed within the vacuum transfer chamber 102, the footprint of the processing apparatus can be reduced.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: October 22, 2002
    Assignee: Tokyo Electron Limited
    Inventors: Masahito Sugiura, Hiroshi Shinriki, Hideki Kiryu, Shintaro Aoyama
  • Patent number: 6428850
    Abstract: A single-substrate-processing CVD apparatus is used for forming a BST thin film on a semiconductor wafer while supplying a first process gas containing a mixture of Ba(thd)2 and Sr(thd)2, and a second process gas containing Ti(O-iPr)(thd)2 or Ti(thd)2. Precursors of Ba and Sr have lower activation energies and higher resistivities than precursors of Ti. The first and second process gases are supplied from a shower head which has a group of first spouting holes for spouting the first process gas and a group of second spouting holes for spouting the second process gas. The group of the second spouting holes are designed to have diameters gradually decreasing in radial directions outward from the center of a shower region, such that the second process gas is supplied at a spouting rate gradually decreasing in radial directions outward from the center.
    Type: Grant
    Filed: July 10, 2000
    Date of Patent: August 6, 2002
    Assignee: Tokyo Electron Limited
    Inventors: Hiroshi Shinriki, Yijun Liu, Masahito Sugiura
  • Publication number: 20010018267
    Abstract: An insulating film consisting of first and second tantalum oxide layers is formed on a semiconductor wafer. First, an amorphous first layer is formed by CVD, and a reforming process for removing organic impurities contained in the first layer is carried out. Then, an amorphous second layer is formed by CVD on the first layer. Then, a reforming process for removing organic impurities contained in the second layer is carried out by supplying a process gas containing ozone into a process chamber while heating the wafer to a temperature lower than a crystallizing temperature over a certain period. Further, within the same process chamber, the wafer is successively heated to a second temperature higher than the crystallizing temperature, followed by cooling the wafer to a temperature lower than the crystallizing temperature so as to crystallize the first and second layers simultaneously.
    Type: Application
    Filed: March 1, 2001
    Publication date: August 30, 2001
    Inventors: Hiroshi Shinriki, Masahito Sugiura
  • Patent number: 6232248
    Abstract: An insulating film consisting of first and second tantalum oxide layers is formed on a semiconductor wafer. First, an amorphous first layer is formed by CVD, and a reforming process for removing organic impurities contained in the first layer is carried out. Then, an amorphous second layer is formed by CVD on the first layer. Then, a reforming process for removing organic impurities contained in the second layer is carried out by supplying a process gas containing ozone into a process chamber while heating the wafer to a temperature lower than a crystallizing temperature over a certain period. Further, within the same process chamber, the wafer is successively heated to a second temperature higher than the crystallizing temperature, followed by cooling the wafer to a temperature lower than the crystallizing temperature so as to crystallize the first and second layers simultaneously.
    Type: Grant
    Filed: June 18, 1999
    Date of Patent: May 15, 2001
    Assignee: Tokyo Electron Limited
    Inventors: Hiroshi Shinriki, Masahito Sugiura
  • Patent number: 6143081
    Abstract: A film forming/modifying system includes a film forming apparatus which has an alcohol supply unit and forms a metal oxide film on a semiconductor wafer in a vacuum atmosphere in which a vaporized metal oxide film material and a vaporized alcohol exist, a film modifying apparatus which has a UV irradiation unit for irradiating a UV ray on ozone to generate active oxygen atoms, and modifies the metal oxide film by exposing the metal oxide film to the active oxygen atoms in a vacuum atmosphere, and a common transfer chamber commonly coupled to the film forming apparatus and the film modifying apparatus to transfer the target process object between the film forming apparatus and the film modifying apparatus while maintaining the vacuum state.
    Type: Grant
    Filed: July 8, 1997
    Date of Patent: November 7, 2000
    Assignee: Tokyo Electron Limited
    Inventors: Hiroshi Shinriki, Masahito Sugiura
  • Patent number: 6126753
    Abstract: A single-substrate-processing CVD apparatus is used for forming a BST thin film on a semiconductor wafer while supplying a first process gas containing a mixture of Ba(thd).sub.2 and Sr(thd).sub.2, and a second process gas containing Ti(O-iPr)(thd).sub.2 or Ti(thd).sub.2. Precursors of Ba and Sr have lower activation energies and higher resistivities than precursors of Ti. The first and second process gases are supplied from a shower head which has a group of first spouting holes for spouting the first process gas and a group of second spouting holes for spouting the second process gas. The group of the second spouting holes are designed to have diameters gradually decreasing in radial directions outward from the center of a shower region, such that the second process gas is supplied at a spouting rate gradually decreasing in radial directions outward from the center.
    Type: Grant
    Filed: May 12, 1999
    Date of Patent: October 3, 2000
    Assignee: Tokyo Electron Limited
    Inventors: Hiroshi Shinriki, Yijun Liu, Masahito Sugiura
  • Patent number: 6063703
    Abstract: A metal interconnection is prepared by forming an underlying metal film of high melting point metal such as Ti and/or high melting point metal compound such as TiN layers above a semiconductor substrate, plasma etching the surface of the underlying metal film in a gas atmosphere containing chloride, and forming an interconnecting metal film such as Al, Cu, Au and Ag on the underlying metal film. Alternatively, a metal interconnection is prepared by forming an insulating film above a semiconductor substrate, forming connecting holes in the insulating film, forming an underlying metal film such as TiN on the insulating film and the bottom and side wall of the connection holes by a CVD process under controlled conditions, and forming an interconnecting metal film such as Al on the underlying metal film. The TiN film has (111) preferential orientation and the aluminum film has (111) preferential orientation, smooth surface and effective coverage.
    Type: Grant
    Filed: May 19, 1998
    Date of Patent: May 16, 2000
    Assignee: Kawasaki Steel Corporation
    Inventors: Hiroshi Shinriki, Takeshi Kaizuka, Nobuyuki Takeyasu, Tomohiro Ohta, Eiichi Kondoh, Hiroshi Yamamoto, Tomoharu Katagiri, Tadashi Nakano, Yumiko Kawano
  • Patent number: 6001729
    Abstract: A semiconductor device with a contact structure includes a silicon substrate, a diffusion region formed in a surface of the silicon substrate, a silicide film of a high melting point metal deposited on the diffusion region, an insulating film formed on the silicon substrate, a contact hole formed in the insulating film such that the silicide film is exposed at a bottom of the contact hole, an anti-diffusion film formed on at least the exposed surface of the silicide film at the bottom of the contact film, a plug formed in the contact hole by selective Al-CVD, and a metal wiring formed on the insulating film. The metal wiring is electrically connected to the diffusion region by the plug, the anti-diffusion film and the silicide film. The anti-diffusion film is formed by nitriding the surface of the silicide film such that only the grain boundaries of the grains of the silicide film are nitrided.
    Type: Grant
    Filed: August 14, 1998
    Date of Patent: December 14, 1999
    Assignee: Kawasaki Steel Corporation
    Inventors: Hiroshi Shinriki, Takayuki Komiya, Hiroshi Yamamoto
  • Patent number: 5973402
    Abstract: A metal interconnection is prepared by forming an underlying metal film of high melting point metal such as Ti and/or high melting point metal compound such as TiN layers above a semiconductor substrate, plasma etching the surface of the underlying metal film in a gas atmosphere containing chloride, and forming an interconnecting metal film such as Al, Cu, Au and Ag on the underlying metal film. Alternatively, a metal interconnection is prepared by forming an insulating film above a semiconductor substrate, forming connection holes in the insulating film, forming an underlying metal film such as TiN on the insulating film and the bottom and side wall of the connection holes by a CVD process under controlled conditions, and forming an interconnecting metal film such as Al on the underlying metal film. The TiN film has (111) preferential orientation and the aluminum film has (111) preferential orientation, smooth surface and effective coverage.
    Type: Grant
    Filed: January 30, 1997
    Date of Patent: October 26, 1999
    Assignee: Kawasaki Steel Corporation
    Inventors: Hiroshi Shinriki, Takeshi Kaizuka, Nobuyuki Takeyasu, Tomohiro Ohta, Eiichi Kondoh, Hiroshi Yamamoto, Tomoharu Katagiri, Tadashi Nakano, Yumiko Kawano
  • Patent number: 5834846
    Abstract: A semiconductor device with a contact structure includes a silicon substrate, a diffusion region formed in a surface of the silicon substrate, a silicide film of a high melting point metal deposited on the diffusion region, an insulating film formed on the silicon substrate, a contact hole formed in the insulating film such that the silicide film is exposed at a bottom of the contact hole, an anti-diffusion film formed on at least the exposed surface of the silicide film at the bottom of the contact film, a plug formed in the contact hole by selective Al--CVD, and a metal wiring formed on the insulating film. The metal wiring is electrically connected to the diffusion region by the plug, the anti-diffusion film and the silicide film. The anti-diffusion film is formed by nitriding the surface of the silicide film such that only the grain boundaries of the grains of the silicide film are nitrided.
    Type: Grant
    Filed: August 23, 1995
    Date of Patent: November 10, 1998
    Assignee: Kawasaki Steel Corporation
    Inventors: Hiroshi Shinriki, Takayuki Komiya, Hiroshi Yamamoto
  • Patent number: 5679974
    Abstract: An antifuse element for a semiconductor device, comprising a bottom electrode made from a conductive material containing a refractory metal and a top electrode made from a conductive material containing a fusible metal. The fusible metal is Al, Al alloy, Cu or Ag. The Al alloy contains at least Si, Cu, Sc, Pd, Ti, Ta or Nb. The refractory metal is Ti, Zr, Hf, V, Nb, Ta, Cr, Mo or W. Silicides are most preferable as the refractory metal. The semiconductor device is programmed by making the top electrode negative or positive and by applying a breakdown voltage between the bottom and top electrodes so as to break down an antifuse material layer, thereby obtaining a filament. The filament is made from the fusible metal from the top electrode and the refractory metal from the bottom electrode. Thus, the filament has a low resistance, and a good EM resistance.
    Type: Grant
    Filed: December 5, 1994
    Date of Patent: October 21, 1997
    Assignee: Kawasaki Steel Corporation
    Inventors: Hiroshi Shinriki, Yoshimitsu Tamura, Tomohiro Ohta
  • Patent number: 5652180
    Abstract: A semiconductor device with a contact structure includes a silicon substrate, a diffusion region formed in a surface of the silicon substrate, a silicide film of high melting point metal deposited on the diffusion region, an insulating film formed on the silicon substrate, a contact hole formed in the insulating film such that the silicide film is exposed at a bottom of the contact hole, an anti-diffusion film formed on the exposed surface of the silicide film at the bottom of the contact film, a plug formed in the contact hole by a selective Al CVD, and a metal wiring formed on the insulating film such that the metal wiring is electrically connected to the diffusion region by means of the plug, anti-diffusion film and silicide film. The anti-diffusion film may be formed by nitriding the surface of the silicide film.
    Type: Grant
    Filed: June 24, 1994
    Date of Patent: July 29, 1997
    Assignee: Kawasaki Steel Corporation
    Inventors: Hiroshi Shinriki, Hiroshi Yamamoto, Nobuyuki Takeyasu, Takayuki Komiya, Tomohiro Ohta
  • Patent number: 5641985
    Abstract: Antifuse elements for a semiconductor device comprise a bottom electrode, a top electrode, and an antifuse material layer. The bottom electrode is formed of a conductive material having an amorphous structure. The conductive material contains such elements as W, Ti, or a compound thereof. Since there is no grain boundary on the surface of the bottom electrode having an amorphous structure, any sharp protrusions are diminished to promote the smoothness. The antifuse material film is mounted on the surface of the bottom electrode. The bottom electrode contains such elements having an excellent EM resistance as W, Mo. These elements are also to be contained in a filament which is formed after programming.
    Type: Grant
    Filed: December 5, 1994
    Date of Patent: June 24, 1997
    Assignee: Kawasaki Steel Corporation
    Inventors: Yoshimitsu Tamura, Hiroshi Shinriki, Tomohiro Ohta