Patents by Inventor Hiroshi Toyoshima
Hiroshi Toyoshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7888788Abstract: Mutual inductance from an external output signal system to an external input signal system, in which parallel input/output operation is enabled, is reduced. A semiconductor integrated circuit has a plurality of external connection terminals facing a package substrate, and has an external input terminal and an external output terminal, in which parallel input/output operation is enabled, as part of the external connection terminals. The package substrate has a plurality of wiring layers for electrically connecting between the external connection terminals and module terminals corresponding to each other. A first wiring layer facing the semiconductor integrated circuit has a major wiring for connecting between the external input terminal and a module terminal corresponding to each other, and a second wiring layer in which the module terminals are formed has a major wiring for connecting between an external output terminal and a module terminal corresponding to each other.Type: GrantFiled: August 20, 2010Date of Patent: February 15, 2011Assignee: Renesas Electronics CorporationInventors: Yasuhiro Yoshikawa, Motoo Suwa, Hiroshi Toyoshima
-
Publication number: 20100314761Abstract: Mutual inductance from an external output signal system to an external input signal system, in which parallel input/output operation is enabled, is reduced. A semiconductor integrated circuit has a plurality of external connection terminals facing a package substrate, and has an external input terminal and an external output terminal, in which parallel input/output operation is enabled, as part of the external connection terminals. The package substrate has a plurality of wiring layers for electrically connecting between the external connection terminals and module terminals corresponding to each other. A first wiring layer facing the semiconductor integrated circuit has a major wiring for connecting between the external input terminal and a module terminal corresponding to each other, and a second wiring layer in which the module terminals are formed has a major wiring for connecting between an external output terminal and a module terminal corresponding to each other.Type: ApplicationFiled: August 20, 2010Publication date: December 16, 2010Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yasuhiro Yoshikawa, Motoo Suwa, Hiroshi Toyoshima
-
Patent number: 7800214Abstract: Mutual inductance from an external output signal system to an external input signal system, in which parallel input/output operation is enabled, is reduced. A semiconductor integrated circuit has a plurality of external connection terminals facing a package substrate, and has an external input terminal and an external output terminal, in which parallel input/output operation is enabled, as part of the external connection terminals. The package substrate has a plurality of wiring layers for electrically connecting between the external connection terminals and module terminals corresponding to each other. A first wiring layer facing the semiconductor integrated circuit has a major wiring for connecting between the external input terminal and a module terminal corresponding to each other, and a second wiring layer in which the module terminals are formed has a major wiring for connecting between an external output terminal and a module terminal corresponding to each other.Type: GrantFiled: November 27, 2006Date of Patent: September 21, 2010Assignee: Renensas Electronics CorporationInventors: Yasuhiro Yoshikawa, Motoo Suwa, Hiroshi Toyoshima
-
Patent number: 7443212Abstract: The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.Type: GrantFiled: August 9, 2007Date of Patent: October 28, 2008Assignee: Renesas Technology Corp.Inventors: Atsuhiro Hayashi, Takemi Negishi, Hiroshi Toyoshima
-
Publication number: 20080211548Abstract: The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.Type: ApplicationFiled: April 29, 2008Publication date: September 4, 2008Inventors: Atsuhiro Hayashi, Takemi Negishi, Hiroshi Toyoshima
-
Patent number: 7320482Abstract: The invention intends to provide a technique that achieves a sufficient phase margin with ease. The circuit includes a power supply circuit that is formed with a phase compensating resistor and a phase compensating capacitor, between a second input terminal of a differential amplifier and a low supply voltage. Thereby, the first pole frequency in the overall gain is determined by the first pole frequency in the voltage-dividing resistor stage in the Bode diagram for the pole/zero compensation, which is shifted to a lower frequency. Also, the zero point cancels the first pole frequency in the differential amplifier stage, which reduces the phase delay to secure the phase margin.Type: GrantFiled: April 3, 2007Date of Patent: January 22, 2008Assignees: Hitachi ULSI Systems Co., Ltd., Renesas Technology Corp.Inventors: Hiroshi Toyoshima, Masahiko Nishiyama
-
Publication number: 20070296470Abstract: The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.Type: ApplicationFiled: August 9, 2007Publication date: December 27, 2007Inventors: Atsuhiro Hayashi, Takemi Negishi, Hiroshi Toyoshima
-
Patent number: 7262643Abstract: The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.Type: GrantFiled: July 17, 2006Date of Patent: August 28, 2007Assignee: Renesas Technology Corp.Inventors: Atsuhiro Hayashi, Takemi Negishi, Hiroshi Toyoshima
-
Publication number: 20070176580Abstract: The invention intends to provide a technique that achieves a sufficient phase margin with ease. The circuit includes a power supply circuit that is formed with a phase compensating resistor and a phase compensating capacitor, between a second input terminal of a differential amplifier and a low supply voltage. Thereby, the first pole frequency in the overall gain is determined by the first pole frequency in the voltage-dividing resistor stage in the Bode diagram for the pole/zero compensation, which is shifted to a lower frequency. Also, the zero point cancels the first pole frequency in the differential amplifier stage, which reduces the phase delay to secure the phase margin.Type: ApplicationFiled: April 3, 2007Publication date: August 2, 2007Inventors: Hiroshi Toyoshima, Masahiko Nishiyama
-
Publication number: 20070120245Abstract: Mutual inductance from an external output signal system to an external input signal system, in which parallel input/output operation is enabled, is reduced. A semiconductor integrated circuit has a plurality of external connection terminals facing a package substrate, and has an external input terminal and an external output terminal, in which parallel input/output operation is enabled, as part of the external connection terminals. The package substrate has a plurality of wiring layers for electrically connecting between the external connection terminals and module terminals corresponding to each other. A first wiring layer facing the semiconductor integrated circuit has a major wiring for connecting between the external input terminal and a module terminal corresponding to each other, and a second wiring layer in which the module terminals are formed has a major wiring for connecting between an external output terminal and a module terminal corresponding to each other.Type: ApplicationFiled: November 27, 2006Publication date: May 31, 2007Inventors: Yasuhiro YOSHIKAWA, Motoo Suwa, Hiroshi Toyoshima
-
Patent number: 7208924Abstract: The invention intends to provide a technique that achieves a sufficient phase margin with ease. The circuit includes a power supply circuit that is formed with a phase compensating resistor and a phase compensating capacitor, between a second input terminal of a differential amplifier and a low supply voltage. Thereby, the first pole frequency in the overall gain is determined by the first pole frequency in the voltage-dividing resistor stage in the Bode diagram for the pole/zero compensation, which is shifted to a lower frequency. Also, the zero point cancels the first pole frequency in the differential amplifier stage, which reduces the phase delay to secure the phase margin.Type: GrantFiled: June 3, 2003Date of Patent: April 24, 2007Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Hiroshi Toyoshima, Masahiko Nishiyama
-
Patent number: 7176729Abstract: The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.Type: GrantFiled: April 22, 2004Date of Patent: February 13, 2007Assignee: Renesas Technology Corp.Inventors: Atsuhiro Hayashi, Takemi Negishi, Hiroshi Toyoshima
-
Publication number: 20060279340Abstract: A dummy MOSFET is provided which is connected in common with the gate of an N channel output MOSFET that constitutes a CMOS output circuit and which is set so as to have a gate capacitance corresponding to a difference between a gate capacitance of a P channel output MOSFET that constitutes the CMOS output circuit and a gate capacitance of the N channel output MOSFET. An input capacitance of the N channel output MOSFET and an input capacitance of the P channel output MOSFET are set equal to each other.Type: ApplicationFiled: June 12, 2006Publication date: December 14, 2006Inventor: Hiroshi Toyoshima
-
Publication number: 20060255842Abstract: The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.Type: ApplicationFiled: July 17, 2006Publication date: November 16, 2006Inventors: Atsuhiro Hayashi, Takemi Negishi, Hiroshi Toyoshima
-
Patent number: 6909653Abstract: The invention provides a semiconductor integrated circuit device having a signal transmission path realizing high speed and low power consumption with a simple configuration. The device has a signal transmission path for transmitting a signal by discharging one of first signal lines corresponding to complementary input signals in a plurality of first signal lines precharged by a precharge circuit, and a self reset circuit for detecting the discharge level of the pair of signal lines corresponding to the complementary signals out of the plurality of first signal lines and operating the precharge circuit at a timing later than the period of discharging.Type: GrantFiled: June 3, 2003Date of Patent: June 21, 2005Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Daisuke Shimadu, Hiroshi Toyoshima, Masahiko Nishiyama
-
Publication number: 20050047232Abstract: The invention provides a semiconductor integrated circuit device having a signal transmission path realizing high speed and low power consumption with a simple configuration. The device has a signal transmission path for transmitting a signal by discharging one of first signal lines corresponding to complementary input signals in a plurality of first signal lines precharged by a precharge circuit, and a self reset circuit for detecting the discharge level of the pair of signal lines corresponding to the complementary signals out of the plurality of first signal lines and operating the precharge circuit at a timing later than the period of discharging.Type: ApplicationFiled: June 3, 2003Publication date: March 3, 2005Inventors: Daisuke Shimadu, Hiroshi Toyoshima, Masahiko Nishiyama
-
Patent number: 6835971Abstract: A semiconductor integrated circuit device, which is intended to prevent the characteristic degradation, includes multiple limiter circuits which are laid out by being scattered across a semiconductor substrate to produce an internal power voltage of a certain voltage level. Each limiter circuit is laid out so as to have its transistor formation area located just beneath the formation area of a bump electrode which puts in an externally supplied power voltage. The scattered layout of limiter circuits avoids the concentration of current to one limiter circuit and alleviates the harmful heat-up of the limiter circuits and their periphery. The shorter wiring length from the bump electrode to the transistor results in a smaller wiring resistance, alleviating the power voltage drop on the wiring.Type: GrantFiled: January 31, 2003Date of Patent: December 28, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroshi Toyoshima, Atsuhiro Hayashi, Takemi Negishi, Takashi Uehara
-
Publication number: 20040251940Abstract: The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.Type: ApplicationFiled: April 22, 2004Publication date: December 16, 2004Inventors: Atsuhiro Hayashi, Takemi Negishi, Hiroshi Toyoshima
-
Publication number: 20030235058Abstract: The invention intends to provide a technique that achieves a sufficient phase margin with ease. The circuit includes a power supply circuit that is formed with a phase compensating resistor and a phase compensating capacitor, between a second input terminal of a differential amplifier and a low supply voltage. Thereby, the first pole frequency in the overall gain is determined by the first pole frequency in the voltage-dividing resistor stage in the Bode diagram for the pole/zero compensation, which is shifted to a lower frequency. Also, the zero point cancels the first pole frequency in the differential amplifier stage, which reduces the phase delay to secure the phase margin.Type: ApplicationFiled: June 3, 2003Publication date: December 25, 2003Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroshi Toyoshima, Masahiko Nishiyama
-
Publication number: 20030151100Abstract: A semiconductor integrated circuit device, which is intended to prevent the characteristic degradation, includes multiple limiter circuits which are laid out by being scattered across a semiconductor substrate to produce an internal power voltage of a certain voltage level. Each limiter circuit is laid out so as to have its transistor formation area located just beneath the formation area of a bump electrode which puts in an externally supplied power voltage. The scattered layout of limiter circuits avoids the concentration of current to one limiter circuit and alleviates the harmful heat-up of the limiter circuits and their periphery. The shorter wiring length from the bump electrode to the transistor results in a smaller wiring resistance, alleviating the power voltage drop on the wiring.Type: ApplicationFiled: January 31, 2003Publication date: August 14, 2003Applicant: Hitachi, Ltd.Inventors: Hiroshi Toyoshima, Atsuhiro Hayashi, Takemi Negishi, Takashi Uehara