Patents by Inventor Hiroshi Yamasaki

Hiroshi Yamasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210220429
    Abstract: [Problem] The present invention addresses the problem of providing an effective method for treating ulcers or fistulas of the intestinal tract that are caused by inflammatory bowel disease, etc. [Solution] Provided is a pharmaceutical composition for treating or preventing ulcers or fistulas in the intestinal tract, the pharmaceutical composition containing a therapeutically effective amount of a self-assembling peptide.
    Type: Application
    Filed: October 4, 2019
    Publication date: July 22, 2021
    Inventors: Hiroshi Yamasaki, Keichi Mitsuyama, Toshihiro Araki
  • Publication number: 20210143258
    Abstract: A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings.
    Type: Application
    Filed: January 21, 2021
    Publication date: May 13, 2021
    Inventors: Hiroyuki Tomomatsu, Sameer Pendharkar, Hiroshi Yamasaki
  • Publication number: 20210057803
    Abstract: According to an aspect, a wireless communication device is wearable on a living body. The wireless communication device includes an antenna and an attachment. The antenna has a first conductor, a second conductor, at least one third conductor, a fourth conductor, and a feeding line. The first conductor and the second conductor are opposed to each other in a first axis. The third conductor is positioned between the first conductor and the second conductor. The third conductor extends in the first axis. The fourth conductor extends in the first axis. The feeding line is electromagnetically connected to any one of at least one third conductor. The first conductor and the second conductor are capacitively connected to each other through the third conductor. The attachment allows the fourth conductor to be opposed to the living body.
    Type: Application
    Filed: November 2, 2018
    Publication date: February 25, 2021
    Inventors: Nobuki HIRAMATSU, Hiroshi UCHIMURA, Masato FUJISHIRO, Hiroshi YAMASAKI, Shotaro SUGITA, Takahiro WATANABE
  • Publication number: 20210057799
    Abstract: An antenna is installed on an installation surface of a wheel. The antenna includes a first conductor, a second conductor, one or more third conductors, a fourth conductor, and a feeding line. The first conductor and the second conductor face each other in a first axis. The one or more third conductors are located between the first conductor and the second conductor and extend in the first axis. The fourth conductor is connected to the first conductor and the second conductor and extends in the first axis. The feeding line is electromagnetically connected to the third conductor. The first conductor and the second conductor are capacitively connected via the third conductor. A surface of the fourth conductor faces the installation surface of the wheel in a second axis perpendicular to the first axis.
    Type: Application
    Filed: January 7, 2019
    Publication date: February 25, 2021
    Inventors: Shinji ISOYAMA, Hiroshi UCHIMURA, Hiroshi YAMASAKI
  • Patent number: 10903320
    Abstract: A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: January 26, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hiroyuki Tomomatsu, Sameer Pendharkar, Hiroshi Yamasaki
  • Publication number: 20200364661
    Abstract: A server uses a travel history of an electric-powered vehicle to estimate the deterioration state of a battery, and stores the estimated deterioration state in association with information for identifying the electric-powered vehicle. When a transmission request for deterioration information is executed at a user terminal, the server transmits the deterioration information to the user terminal. When a shop terminal receives information on a replacement condition for the battery from the user terminal, the shop terminal transmits, to the user terminal, inventory information corresponding to a replacement battery that satisfies the replacement condition.
    Type: Application
    Filed: April 6, 2020
    Publication date: November 19, 2020
    Inventor: Hiroshi YAMASAKI
  • Publication number: 20200350687
    Abstract: A wireless communication device includes an antenna and is used for storage as an electrical conductive body. The antenna includes a first conductor and a second conductor, one or more third conductors, a fourth conductor, and a feeding line. The first conductor and the second conductor face each other in a first axis. The one or more third conductors are located between the first conductor and the second conductor and extend in the first axis. The fourth conductor is connected to the first conductor and the second conductor and extends in the first axis. The feeding line is connected to any one of the third conductors. The first conductor and the second conductor are capacitively coupled to each other via the third conductor. The fourth conductor faces a conductor part of the storage.
    Type: Application
    Filed: January 7, 2019
    Publication date: November 5, 2020
    Inventors: Masato FUJISHIRO, Sunao HASHIMOTO, Nobuki HIRAMATSU, Jun KITAKADO, Hiroshi UCHIMURA, Shinji ISOYAMA, Susumu KASHIWASE, Hiroshi YAMASAKI, Masamichi YONEHARA, Yasuhiko FUKUOKA, Takanori IKUTA, Toi KANDA
  • Patent number: 10784536
    Abstract: A method including a step of preparing a positive electrode including a positive electrode mixture layer, a negative electrode including a negative electrode mixture layer, and a nonaqueous electrolyte; and a step of accommodating the positive electrode, the negative electrode, and the nonaqueous electrolyte in a battery case. The nonaqueous electrolyte contains a compound (I) represented by the following formula (I) LiO3S—R—SO3Li (wherein R represents a linear hydrocarbon group having 1 to 10 carbon atoms). When a BET specific surface area of the negative electrode mixture layer is represented by X (m2/g) and when an amount of the compound (I) with respect to the total amount of the nonaqueous electrolyte is represented by Y (mass %), the following relationships 3?X?4.3, 0.2?Y?0.4, and (Y/X)?0.093 are satisfied.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: September 22, 2020
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hiroshi Yamasaki, Tatsuya Hashimoto
  • Patent number: 10707323
    Abstract: Metal contact openings are etched in the barrier layer of a group III-N HEMT with a first gas combination that etches down into the barrier layer, and a second gas combination that etches further down into the barrier layer to a depth that lies above the top surface of a channel layer that touches and lies below the barrier layer.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: July 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yoshikazu Kondo, Shoji Wada, Hiroshi Yamasaki, Masahiro Iwamoto
  • Patent number: 10511057
    Abstract: Provided is a method for producing a non-aqueous electrolyte secondary battery with which resistance increase is inhibited during high-temperature storage while good battery properties are retained. The production method of this invention comprises a step of obtaining a positive electrode, a negative electrode and a non-aqueous electrolyte; and a step of placing the positive electrode, the negative electrode and the non-aqueous electrolyte in a battery case. Herein, the non-aqueous electrolyte comprises a fluorine atom-containing supporting salt and a benzothiophene oxide.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: December 17, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hiroshi Yamasaki, Tomoko Nagao, Tomohiro Nakano, Tatsuya Hashimoto
  • Patent number: 10510847
    Abstract: A transistor device includes a field plate extending from a source contact layer and defining an opening above a gate metal layer. Coplanar with the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. Meanwhile, the opening allows a gate runner layer above the field plate to access and connect to the gate metal layer, which helps reduce the resistance of the gate structure. By vertically overlapping the metal gate layer, the field plate, and the gate runner layer, the transistor device may achieve fast switching performance without incurring any size penalty.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: December 17, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroyuki Tomomatsu, Hiroshi Yamasaki, Sameer Pendharkar
  • Patent number: 10493792
    Abstract: A processing apparatus for performing not only cutting and drawing, but also other processing, and a cartridge used for the processing apparatus are provided. The processing apparatus includes a first cartridge including: a first processing tool to form a machining mark by grinding or cutting a surface of a sheet-like object; an actuator to operate by an external power supply and drive the first processing tool; and a first housing to accommodate the first processing tool where a tip of the first processing tool is exposed and accommodate the actuator. The processing apparatus also includes a carriage including a mounting section which the first cartridge is detachably mounted; a transfer mechanism to move the object and the carriage relatively to each other; and a control circuit to control driving of the transfer mechanism to form the machining mark on the surface of the object by the first processing tool.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: December 3, 2019
    Assignee: BROTHER KOGYO KABUSHIKI KAISHA
    Inventors: Hironori Matsushita, Hiroshi Yamasaki
  • Publication number: 20190288090
    Abstract: Metal contact openings are etched in the barrier layer of a group III-N HEMT with a first gas combination that etches down into the barrier layer, and a second gas combination that etches further down into the barrier layer to a depth that lies above the top surface of a channel layer that touches and lies below the barrier layer.
    Type: Application
    Filed: May 23, 2019
    Publication date: September 19, 2019
    Inventors: Yoshikazu Kondo, Shoji Wada, Hiroshi Yamasaki, Masahiro Iwamoto
  • Publication number: 20190245047
    Abstract: A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings.
    Type: Application
    Filed: April 15, 2019
    Publication date: August 8, 2019
    Inventors: Hiroyuki Tomomatsu, Sameer Pendharkar, Hiroshi Yamasaki
  • Patent number: 10374057
    Abstract: Metal contact openings are etched in the barrier layer of a group III-N HEMT with a first gas combination that etches down into the barrier layer, and a second gas combination that etches further down into the barrier layer to a depth that lies above the top surface of a channel layer that touches and lies below the barrier layer.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: August 6, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yoshikazu Kondo, Shoji Wada, Hiroshi Yamasaki, Masahiro Iwamoto
  • Patent number: 10263085
    Abstract: A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: April 16, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hiroyuki Tomomatsu, Sameer Pendharkar, Hiroshi Yamasaki
  • Publication number: 20190109195
    Abstract: A transistor device includes a field plate extending from a source contact layer and defining an opening above a gate metal layer. Coplanar with the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. Meanwhile, the opening allows a gate runner layer above the field plate to access and connect to the gate metal layer, which helps reduce the resistance of the gate structure. By vertically overlapping the metal gate layer, the field plate, and the gate runner layer, the transistor device may achieve fast switching performance without incurring any size penalty.
    Type: Application
    Filed: December 7, 2018
    Publication date: April 11, 2019
    Inventors: Hiroyuki Tomomatsu, Hiroshi Yamasaki, Sameer Pendharkar
  • Patent number: 10186589
    Abstract: A transistor device includes a field plate extending from a source contact layer and defining an opening above a gate metal layer. Coplanar with the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. Meanwhile, the opening allows a gate runner layer above the field plate to access and connect to the gate metal layer, which helps reduce the resistance of the gate structure. By vertically overlapping the metal gate layer, the field plate, and the gate runner layer, the transistor device may achieve fast switching performance without incurring any size penalty.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: January 22, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroyuki Tomomatsu, Hiroshi Yamasaki, Sameer Pendharkar
  • Publication number: 20190008419
    Abstract: A rehabilitation evaluation apparatus includes a sensor signal acquisition unit configured to acquire a sensor signal output from a detection sensor, a selection unit configured to select at least one myoelectric signal having a correlation with the sensor signal acquired by the sensor signal acquisition unit from among the plurality of second myoelectric signals on the second-side part acquired by the myoelectric-signal acquisition unit, and a similarity output unit configured to select a first myoelectric signal that has been output from a myoelectric sensor attached in a place that is left-right symmetric to a place of the myoelectric sensor that has output the second correlated myoelectric signal selected by the selection unit from among a plurality of first myoelectric signals on the first-side part acquired by the myoelectric-signal acquisition unit, calculate a similarity between these correlated myoelectric signals, and outputs the calculated similarity.
    Type: Application
    Filed: July 5, 2018
    Publication date: January 10, 2019
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shintaro YOSHIZAWA, Hitoshi YAMADA, Alvaro Costa GARCIA, Hiroshi YAMASAKI, Matti Sakari ITKONEN, Shingo SHIMODA
  • Publication number: 20180358258
    Abstract: A method of forming an integrated circuit includes forming ?1 hard mask layer on a device layer on a BOX layer of a SOI substrate. A patterned masking layer is used for a trench etch to simultaneously form larger and smaller area trenches through the hard mask layer, device layer and the BOX layer. A dielectric liner is formed for lining the larger and smaller area trenches. A dielectric layer is deposited for completely filling the smaller area trenches and only partially filling the larger area trenches. The larger area trenches are bottom etched through the dielectric layer to provide a top side contact to the handle portion. The handle portion at a bottom of the larger area trenches is implanted to form a handle contact, and the larger area trenches are completely filled with an electrically conductive layer to form a top side ohmic contact to the handle contact.
    Type: Application
    Filed: June 9, 2017
    Publication date: December 13, 2018
    Inventors: ZACHARY K. LEE, ROBERT GRAHAM SHAW, HIDEAKI KAWAHARA, ASAD MAHMOOD HAIDER, YUJI MIZUGUCHI, HIROSHI YAMASAKI, ABBAS ALI, BRIAN GOODLIN