Abstract: A semiconductor device includes an interrupt control circuit that receives a plurality of interrupt signals from the circuit blocks and outputs an interrupt request to the processor, and an interrupt monitoring circuit that corresponds to one of the interrupt signals and includes a setting circuit for setting a monitoring type and first and second monitoring periods. If the monitoring type indicates an asserted state of the interrupt signal, the interrupt monitoring circuit monitors the asserted state. If a first duration of the continuous asserted state exceeds the first monitoring period, the interrupt monitoring circuit detects the state as a failure. If the monitoring type indicates a negated state of the interrupt signal, the interrupt monitoring circuit monitors the negated state. If a second duration of the continuous negated state exceeds the second monitoring period, the interrupt monitoring circuit detects the state as a failure.

Abstract: A semiconductor device includes an interrupt control circuit that receives a plurality of interrupt signals from the circuit blocks and outputs an interrupt request to the processor, and an interrupt monitoring circuit that corresponds to one of the interrupt signals and includes a setting circuit for setting a monitoring type and first and second monitoring periods. If the monitoring type indicates an asserted state of the interrupt signal, the interrupt monitoring circuit monitors the asserted state. If a first duration of the continuous asserted state exceeds the first monitoring period, the interrupt monitoring circuit detects the state as a failure. If the monitoring type indicates a negated state of the interrupt signal, the interrupt monitoring circuit monitors the negated state. If a second duration of the continuous negated state exceeds the second monitoring period, the interrupt monitoring circuit detects the state as a failure.

Abstract: A semiconductor device includes an interrupt control circuit that receives a plurality of interrupt signals from the circuit blocks and outputs an interrupt request to the processor, and an interrupt monitoring circuit that corresponds to one of the interrupt signals and includes a setting circuit for setting a monitoring type and first and second monitoring periods. If the monitoring type indicates an asserted state of the interrupt signal, the interrupt monitoring circuit monitors the asserted state. If a first duration of the continuous asserted state exceeds the first monitoring period, the interrupt monitoring circuit detects the state as a failure. If the monitoring type indicates a negated state of the interrupt signal, the interrupt monitoring circuit monitors the negated state. If a second duration of the continuous negated state exceeds the second monitoring period, the interrupt monitoring circuit detects the state as a failure.

Abstract: A semiconductor device includes an address conversion circuit which generates the second address for storing an error detecting code in a memory based on the first address for storing data; a write circuit which writes data at the first address and writes an error detecting code at the second address; and a read circuit which reads data from the first address, reads the error detecting code from the second address, and detects an error based on the data and the error detecting code. The address conversion circuit generates an address as the second address by modifying the value of at least one bit of the first address so as to offset the storing position of the error detecting code to the storing position of the data, and by inverting the value of or permutating the order of the prescribed number of bits among the other bits.

Abstract: A semiconductor device includes an interrupt control circuit that receives a plurality of interrupt signals from the circuit blocks and outputs an interrupt request to the processor, and an interrupt monitoring circuit that corresponds to one of the interrupt signals and includes a setting circuit for setting a monitoring type and first and second monitoring periods. If the monitoring type indicates an asserted state of the interrupt signal, the interrupt monitoring circuit monitors the asserted state. If a first duration of the continuous asserted state exceeds the first monitoring period, the interrupt monitoring circuit detects the state as a failure. If the monitoring type indicates a negated state of the interrupt signal, the interrupt monitoring circuit monitors the negated state. If a second duration of the continuous negated state exceeds the second monitoring period, the interrupt monitoring circuit detects the state as a failure.

Abstract: A semiconductor device includes an interrupt control circuit that receives a plurality of interrupt signals from the circuit blocks and outputs an interrupt request to the processor, and an interrupt monitoring circuit that corresponds to one of the interrupt signals and includes a setting circuit for setting a monitoring type and first and second monitoring periods. If the monitoring type indicates an asserted state of the interrupt signal, the interrupt monitoring circuit monitors the asserted state. If a first duration of the continuous asserted state exceeds the first monitoring period, the interrupt monitoring circuit detects the state as a failure. If the monitoring type indicates a negated state of the interrupt signal, the interrupt monitoring circuit monitors the negated state. If a second duration of the continuous negated state exceeds the second monitoring period, the interrupt monitoring circuit detects the state as a failure.

Abstract: An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.

Abstract: A semiconductor device includes an address conversion circuit which generates the second address for storing an error detecting code in a memory based on the first address for storing data; a write circuit which writes data at the first address and writes an error detecting code at the second address; and a read circuit which reads data from the first address, reads the error detecting code from the second address, and detects an error based on the data and the error detecting code. The address conversion circuit generates an address as the second address by modifying the value of at least one bit of the first address so as to offset the storing position of the error detecting code to the storing position of the data, and by inverting the value of or permutating the order of the prescribed number of bits among the other bits.

Abstract: A variable valve timing control device includes a drive-side rotational body, a driven-side rotational body, a connecting bolt coaxially disposed with a rotary axis and connecting the driven-side rotational body to a camshaft, the connecting bolt formed with an advanced-angle port and a retarded-angle port from an outer circumferential surface of the connecting bolt through an inner space, a valve unit disposed at the inner space of the connecting bolt, and a check valve provided at an upstream in a supplying direction of fluid relative to the valve unit. The check valve includes a seat member formed with at least one circulation port at a position being away from the rotary axis; and a valve body configured to close the circulation port at a downstream in the supplying direction of the fluid relative to the seat member, the valve body including an opening portion about the rotary axis.

Abstract: A semiconductor device 1 includes an image input unit 11 and an image output unit 12. The image input unit 11 receives first image data from a camera 91 and outputs second image data to a memory unit 93 through a shared bus 130. The image output unit 12 receives the second image data stored in the memory unit 93 through the shared bus 130 and outputs third image data to a monitor 92. The third image data is generated by performing an affine-conversion on the first image data. Magnification processing in the affine-conversion is not performed in the image input unit 11. In this way, it is possible to provide an excellent semiconductor device suitable for image processing or the like.

Abstract: A valve opening/closing timing control apparatus includes: a driving side rotator configured to rotate synchronously with a crankshaft of an internal combustion engine; a driven side rotator disposed coaxially with a rotation axis of the driving side rotator and configured to rotate integrally with a valve opening/closing camshaft; a connecting bolt disposed coaxially with the rotation axis to connect the driven side rotator to the camshaft, and having an advanced angle port and a retarded angle port formed to extend from an outer peripheral surface to an inner space thereof, the advanced angle port and the retarded angle port communicating with an advanced angle chamber and a retarded angle chamber between the driving side rotator and the driven side rotator, respectively; and a valve unit disposed in the inner space of the connecting bolt.

Abstract: The detection of a fault of the address signal system in memory access is aimed at. A semiconductor device according to the present invention includes an address conversion circuit which generates the second address for storing an error detecting code in a memory based on the first address for storing data; a write circuit which writes data at the first address and writes an error detecting code at the second address; and a read circuit which reads data from the first address, reads the error detecting code from the second address, and detects an error based on the data and the error detecting code. The address conversion circuit generates an address as the second address by modifying the value of at least one bit of the first address so as to offset the storing position of the error detecting code to the storing position of the data, and by inverting the value of or permutating the order of the prescribed number of bits among the other bits.

Abstract: A valve opening and closing timing control apparatus includes: a driving side rotator configured to rotate synchronously with a crankshaft of an internal combustion engine; a driven side rotator disposed coaxially with a rotation axis of the driving side rotator and configured to rotate integrally with a valve opening and closing camshaft; a phase controller configured to control a relative rotation phase between the driving side rotator and the driven side rotator by supply and discharge of a fluid; and a torsion spring configured to attain a biasing force to displace the relative rotation phase between the driving side rotator and the driven side rotator in a predetermined direction. The driving side rotator is fastened to a cover-shaped plate, and the torsion spring includes a first arm and a second arm.

Abstract: A semiconductor device includes an interrupt control circuit that receives a plurality of interrupt signals from the circuit blocks and outputs an interrupt request to the processor, and an interrupt monitoring circuit that corresponds to one of the interrupt signals and includes a setting circuit for setting a monitoring type and first and second monitoring periods. If the monitoring type indicates an asserted state of the interrupt signal, the interrupt monitoring circuit monitors the asserted state. If a first duration of the continuous asserted state exceeds the first monitoring period, the interrupt monitoring circuit detects the state as a failure. If the monitoring type indicates a negated state of the interrupt signal, the interrupt monitoring circuit monitors the negated state. If a second duration of the continuous negated state exceeds the second monitoring period, the interrupt monitoring circuit detects the state as a failure.

Abstract: A spring holder supporting a torsion spring applying an urging force in a valve opening/closing timing control apparatus is configured to be able to be attached to an appropriate position relative to a driven side rotary body and rotatable in unison. The spring holder includes a seat portion that is connected and fixed to the driven side rotary body, a guide portion that extends along a rotational axis, an alignment portion fitted into an engaging portion of the driven side rotary body and a restricted portion fitted into a restricting portion of the driven side rotary body. A support portion holding an end of the torsion spring is formed in the guide portion.

Abstract: A valve opening and closing timing control device includes: a driving-side rotating body synchronously rotated with a crankshaft of an engine and having a lid member fixed in a direction of the rotational axis; a driven-side rotating body integrally rotated with a camshaft for opening and closing a valve on the same rotational axis; a lock mechanism having a lock member moving in the direction and a lock recessed portion formed inside the lid member and into which the lock member is able to be fitted; and a torsion spring disposed outside the lid member and exerting a biasing force to the driving-side and driven-side rotating bodies, wherein a restricting projection portion for restricting a movement of the torsion spring in the direction is formed in the lid member.

Abstract: A valve opening/closing timing control apparatus includes: a driving side rotator configured to rotate synchronously with a crankshaft of an internal combustion engine; a driven side rotator disposed coaxially with a rotation axis of the driving side rotator so as to rotate integrally with a valve opening and closing camshaft; a connecting bolt disposed coaxially with the rotation axis to connect the driven side rotator to the camshaft and having an advanced angle port and a retarded angle port formed to extend from an outer peripheral surface to an inner space thereof, which respectively communicate with an advanced angle chamber and a retarded angle chamber between the driving side rotator and the driven side rotator; and a valve unit disposed in the inner space of the connecting bolt, in which the valve unit includes a check valve, and the check valve includes an opening plate and a valve plate.

Abstract: A valve opening/closing timing control apparatus includes: a driving side rotator configured to rotate synchronously with a crankshaft of an internal combustion engine; a driven side rotator disposed coaxially with a rotation axis of the driving side rotator and configured to rotate integrally with a valve opening/closing camshaft; a connecting bolt disposed coaxially with the rotation axis to connect the driven side rotator to the camshaft, and having an advanced angle port and a retarded angle port formed to extend from an outer peripheral surface to an inner space thereof, the advanced angle port and the retarded angle port communicating with an advanced angle chamber and a retarded angle chamber between the driving side rotator and the driven side rotator, respectively; and a valve unit disposed in the inner space of the connecting bolt.

Abstract: A valve opening/closing timing control apparatus includes: a driving side rotator configured to rotate synchronously with a crankshaft of an internal combustion engine; a driven side rotator disposed coaxially with a rotation axis of the driving side rotator and configured to rotate integrally with a valve opening/closing camshaft; a connecting bolt disposed coaxially with the rotation axis to connect the driven side rotator to the camshaft, and having an advanced angle port and a retarded angle port formed to extend from an outer peripheral surface to an inner space thereof, the advanced angle port and the retarded angle port communicating with an advanced angle chamber and a retarded angle chamber between the driving side rotator and the driven side rotator, respectively; and a valve unit disposed in the inner space of the connecting bolt.

Abstract: There are provided a cylindrical portion in which a passage for feeding/discharging working fluid to/from a fluid pressure chamber is formed and which is disposed inside a driven-side rotary body, a bolt member that connects the driven-side rotary body to a cam shaft, a valve body body for regulating a flow direction of the working fluid relative to the fluid pressure chamber and a valve accommodating body that accommodates the valve body, the valve body and the valve accommodating body being disposed inside the cylindrical portion, and an urging portion provided on at least one of an upstream side and a downstream side of the valve accommodating body and configured to generate a repulsive force between an other object that regulates a position of the valve accommodating body and the valve accommodating body.