Abstract: The valve opening/closing timing control device includes: a driving rotating body; a driven rotating body; a fixed shaft portion; a fluid pressure chamber; a partitioning portion; and a phase control unit for controlling a rotation phase by supplying/discharging pressurized fluid to/from an advancing chamber or a retarding chamber via an inside of the fixed shaft portion. The driven rotating body has: an inner circumferential member with a cylindrical portion, and a coupling plate portion of the camshaft, the cylindrical portion and the coupling plate portion being integrated with each other; and an outer circumferential member provided with the partitioning portion. The outer circumferential member includes the inner circumferential member in a unified manner so as to have the same rotational axis. The inner circumferential member is formed with an iron-based material. The outer circumferential member is formed with a material that is lighter in weight than the iron-based material.

Abstract: Provided is an image processing device capable of an image processing with using a general-purpose image processing hardware in accordance with video input without mediation of a CPU. The image processing device includes: a storage medium for storing an image data acquired by video inputting unit for acquiring video images; a CPU for a general processing; image processing unit for processing the image data stored in the storage medium; setting unit for determining a processing content of the image processing unit; a command list indicating an order of setting and activating the image processing unit; and command writing unit for setting and activating the image processing unit based on the command list in synchronization with input of the image data from the video inputting unit without mediation of the CPU.

Abstract: Means which enables image conversion in which a plurality of conversion results can be output without once saving all of video-image data, which has been input from image-pickup means, in a storage medium is provided. A single line memory having a plurality of lines is used while switching the role thereof for a reading use by a video-image converting means and a use for inputting image data from the image-pickup means. The image converting means obtains an input image, which is in the line memory, and carries out conversion of the input image based on a conversion specifying means interpreted by an instruction decoder.

Abstract: The valve opening/closing timing control device includes: an advancing chamber and a retarding chamber that are formed by partitioning a fluid pressure chamber that is formed between a driving rotating body and a driven rotating body that is located on an inner circumference side of the driving rotating body so as to be relatively rotatable, with a partitioning portion that is provided on an outer circumference side of the driven rotating body; an advancing channel that is in communication with the advancing chamber; and a retarding channel that is in communication with the retarding chamber. The driven rotating body has a first member and a second member, and the advancing channel and the retarding channel are formed to penetrate through a boundary between the first member and the second member after the first member and the second member have been installed.

Abstract: Provided is an image processing device capable of an image processing with using a general-purpose image processing hardware in accordance with video input without mediation of a CPU. The image processing device includes: a storage medium for storing an image data acquired by video inputting unit for acquiring video images; a CPU for a general processing; image processing unit for processing the image data stored in the storage medium; setting unit for determining a processing content of the image processing unit; a command list indicating an order of setting and activating the image processing unit; and command writing unit for setting and activating the image processing unit based on the command list in synchronization with input of the image data from the video inputting unit without mediation of the CPU.

Abstract: Means which enables image conversion in which a plurality of conversion results can be output without once saving all of video-image data, which has been input from image-pickup means, in a storage medium is provided. A single line memory having a plurality of lines is used while switching the role thereof for a reading use by a video-image converting means and a use for inputting image data from the image-pickup means. The image converting means obtains an input image, which is in the line memory, and carries out conversion of the input image based on a conversion specifying means interpreted by an instruction decoder.

Abstract: A semiconductor device 1 includes an image input unit 11 and an image output unit 12. The image input unit 11 receives first image data from a camera 91 and outputs second image data to a memory unit 93 through a shared bus 130. The image output unit 12 receives the second image data stored in the memory unit 93 through the shared bus 130 and outputs third image data to a monitor 92. The third image data is generated by performing an affine-conversion on the first image data. Magnification processing in the affine-conversion is not performed in the image input unit 11. In this way, it is possible to provide an excellent semiconductor device suitable for image processing or the like.

Abstract: A semiconductor device 1 includes an image input unit 11 and an image output unit 12. The image input unit 11 receives first image data from a camera 91 and outputs second image data to a memory unit 93 through a shared bus 130. The image output unit 12 receives the second image data stored in the memory unit 93 through the shared bus 130 and outputs third image data to a monitor 92. The third image data is generated by performing an affine-conversion on the first image data. Magnification processing in the affine-conversion is not performed in the image input unit 11. In this way, it is possible to provide an excellent semiconductor device suitable for image processing or the like.

Abstract: The present invention is provided to lessen load on a bus in the case of storing image data captured by a plurality of cameras into a semiconductor memory. To a semiconductor integrated circuit, a plurality of cameras and a semiconductor memory can be coupled. The semiconductor integrated circuit includes a plurality of first interfaces, a second interface, a bus, and a plurality of image processing modules. The image processing modules include a process of performing distortion correction on image data in a pre-designated region, and writing the image data in the region subjected to the distortion correction into the semiconductor memory via the bus and the second interface. By excluding image data out of the pre-designated region from an object of distortion correction in the image processing modules, the amount of image data transferred to the semiconductor memory is reduced.

Abstract: The present invention is provided to lessen load on a bus in the case of storing image data captured by a plurality of cameras into a semiconductor memory. To a semiconductor integrated circuit, a plurality of cameras and a semiconductor memory can be coupled. The semiconductor integrated circuit includes a plurality of first interfaces, a second interface, a bus, and a plurality of image processing modules. The image processing modules include a process of performing distortion correction on image data in a pre-designated region, and writing the image data in the region subjected to the distortion correction into the semiconductor memory via the bus and the second interface. By excluding image data out of the pre-designated region from an object of distortion correction in the image processing modules, the amount of image data transferred to the semiconductor memory is reduced.

Abstract: Means which enables image conversion in which a plurality of conversion results can be output without once saving all of video-image data, which has been input from image-pickup means, in a storage medium is provided. A single line memory having a plurality of lines is used while switching the role thereof for a reading use by a video-image converting means and a use for inputting image data from the image-pickup means. The image converting means obtains an input image, which is in the line memory, and carries out conversion of the input image based on a conversion specifying means interpreted by an instruction decoder.

Abstract: A parallel operation histogramming device can handle parallel-input data from a plurality of processors to generate frequency data of a histogram. The processing time for generating frequency data of the histogram is independent of the distribution of histogram values in the input data. The device can also reduce the memory area used for accumulating frequency data of the histogram. The device includes a histogram counter circuit which has a plurality of counters equal in number to the number of histogram bins. The counters count in parallel the number of pieces of data for each type of the operation results from the plurality of processors. The counted values from each counter are accumulated to form the frequencies in a histogram.

Abstract: Means which enables image conversion in which a plurality of conversion results can be output without once saving all of video-image data, which has been input from image-pickup means, in a storage medium is provided. A single line memory having a plurality of lines is used while switching the role thereof for a reading use by a video-image converting means and a use for inputting image data from the image-pickup means. The image converting means obtains an input image, which is in the line memory, and carries out conversion of the input image based on a conversion specifying means interpreted by an instruction decoder.

Abstract: An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.

Abstract: An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.

Abstract: A semiconductor device 1 includes an image input unit 11 and an image output unit 12. The image input unit 11 receives first image data from a camera 91 and outputs second image data to a memory unit 93 through a shared bus 130. The image output unit 12 receives the second image data stored in the memory unit 93 through the shared bus 130 and outputs third image data to a monitor 92. The third image data is generated by performing an affine-conversion on the first image data. Magnification processing in the affine-conversion is not performed in the image input unit 11. In this way, it is possible to provide an excellent semiconductor device suitable for image processing or the like.

Abstract: In a data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.

Abstract: A parallel operation histogramming device can handle parallel-input data from a plurality of processors to generate frequency data of a histogram. The processing time for generating frequency data of the histogram is independent of the distribution of histogram values in the input data. The device can also reduce the memory area used for accumulating frequency data of the histogram. The device includes a histogram counter circuit which has a plurality of counters equal in number to the number of histogram bins. The counters count in parallel the number of pieces of data for each type of the operation results from the plurality of processors. The counted values from each counter are accumulated to form the frequencies in a histogram.

Abstract: To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption.

Abstract: The present invention provides a data processing system having excellent immediacy of interrupting process. Different interrupt request signals are supplied from a circuit module which can be commonly used by a plurality of central processing units to a plurality of interrupt controllers assigned to central processing units, respectively. In response to the input interrupt request signal, each of the interrupt controllers notifies the corresponding central processing unit of an interrupt. The circuit module selects an interrupt controller for supplying an interrupt request signal from the plural interrupt controllers. For example, the circuit module identifies a central processing unit which instructed a start request and supplies an interrupt request signal to an interrupt controller corresponding to the central processing unit. The burden of the interrupting process of the single central processing unit can be lessened.