Abstract: Provided is a method for identifying and suppressing abnormal growth of fibroblasts at an early stage. Provided is a method for identifying the growth state of fibroblasts using as an index the level of expression of ETFB (electron transfer flavoprotein beta subunit), comprising: judging, in cases where the level of expression of ETFB is high, that there is a high probability that fibroblasts are abnormally growing; and judging, in cases where the level of expression of ETFB is low, that there is a high probability that fibroblasts are normally growing. Further, by inhibition of ETFB, abnormal growth of fibroblasts can be suppressed.

Abstract: A transmission apparatus exercises insertion control for inserting a client signal and a stuff byte into a payload area in a frame into which the client signal is to be mapped, and sends the frame after the insertion control. In addition, the transmission apparatus inserts the client signal or the stuff byte in columns of the frame into the payload area except a leading column.

Abstract: An apparatus for mapping multiple lower-speed signal transmission frames to a higher-speed signal transmission frame. The apparatus includes buffers configured to buffer the lower-speed signal transmission frames, determination units configured to determine frequency justification information for the lower-speed signal transmission frames, a barrel shifter configured to receive signals output from the buffers, and a controller configured to control the barrel shifter to map the lower-speed signal transmission frames to the higher-speed signal transmission frame based on external settings for the respective lower-speed signal transmission frames and the frequency justification information determined by the determination units. When the minimum unit of the lower-speed signal transmission frames is a channel, the number of the buffers and the number of the determination units correspond to the maximum number of channels that can be multiplexed in the higher-speed signal transmission frame.

Abstract: A frame transmitting apparatus includes a transmitting unit which transmits, when a change is made to a value in a predetermined field of a frame, the frame including the predetermined field with the changed value a predetermined number of times in succession. A frame receiving apparatus includes a receiving unit which receives the frame and an acceptance processing unit which recognizes the value in the predetermined field of the received frame and conducts acceptance processing. The acceptance processing unit compares, when the value is different from a currently accepted value, the value with an expected value; accepts the value when the value matches the expected value; and accepts, when the value does not match the expected value, the value after receiving the same value the predetermined number of times in succession.

Abstract: A data amount derivation apparatus includes: a first calculator configured to derive, for one series of parallelized mapping signals, amount of data in each frame period for a frame into which the parallelized mapping signals are mapped; and a second calculator configured to sum up amounts of data in N frame periods, where N is an integer, and to derive the resulting summation value as the amount of data to be mapped into the frame, each of the amounts of data in each of the frame periods being derived by the first calculator.

Abstract: An error correction processing circuit, includes: a division circuit that divides input data into a plurality of pieces of a predetermined data length; a plurality of operation circuits that are provided in parallel, and that perform operations of error correction for the plurality of pieces of data divided by the division circuit, respectively; a multiplexing circuit that multiplexes the plurality of pieces of data for which the operations have been performed by the plurality of operation circuits; and an output circuit that outputs the data multiplexed by the multiplexing circuit.

Abstract: An apparatus for mapping multiple lower-speed signal transmission frames to a higher-speed signal transmission frame. The apparatus includes buffers configured to buffer the lower-speed signal transmission frames, determination units configured to determine frequency justification information for the lower-speed signal transmission frames, a barrel shifter configured to receive signals output from the buffers, and a controller configured to control the barrel shifter to map the lower-speed signal transmission frames to the higher-speed signal transmission frame based on external settings for the respective lower-speed signal transmission frames and the frequency justification information determined by the determination units. When the minimum unit of the lower-speed signal transmission frames is a channel, the number of the buffers and the number of the determination units correspond to the maximum number of channels that can be multiplexed in the higher-speed signal transmission frame.

Abstract: A transmission apparatus exercises insertion control for inserting a client signal and a stuff byte into a payload area in a frame into which the client signal is to be mapped, and sends the frame after the insertion control. In addition, the transmission apparatus inserts the client signal or the stuff byte in columns of the frame into the payload area except a leading column.

Abstract: An optimization model analysis apparatus configured with a finite element model generation unit that generates on the basis of a structural configuration of a design model having a 3D shape a finite element model for analyzing acoustic characteristics of the design by a finite element method. The apparatus is configured with a shell model generation unit that generates a model by dividing a surface of the finite element model into a plurality of plate elements having a polygonal shape; an optimization model generation unit that superimposes the shell model on the surface of the finite element model to generate an optimization model; and an optimization model modification unit that displaces nodal points which serve as vertexes of the plate elements in a direction intersecting a plane of the plate elements by displacing at least one of the nodal points in a direction of reducing a thickness of the optimization model.

Abstract: A storage system stores multiple copies of data on physical storage implemented, for example, with multiple disk units. Input/output read requests are received from host systems and distributed in a manner that allows parallel read operations to be conducted over the multiple disk units of the physical storage.

Abstract: A buffer operation method, for use with a buffer organized as a plurality of sections, two or more continuous ones of the sections being defined as a monitor block, the method including: receiving a data packet and dividing the same into a plurality of divisions; storing the divisions in a given one of the sections; moving, in the case where the given section is behind the monitor block, the monitor block so that a tail end thereof corresponds to the given section; monitoring whether the plurality of divisions required for reassembly of the packet are stored in the monitor block; and transferring, once all the required plurality of divisions are collected in the monitor block, the same from the buffer for subsequent reassembly of the packet.

Abstract: A packet transmission apparatus includes a transmission unit dividing input data and transferring segments, which are obtained by adding sequence numbers to the respective pieces of the divided data, a switch unit transferring the segments to one of a plurality of reception units, and a reception unit reconstructing an original input packet from the plurality of segments that arrive from the switch units on the basis of the sequence numbers. The reception unit includes a packet buffer storing segments that arrive from the switch units, a determination unit determining, on the basis of the sequence number, whether the segment stored in the packet buffer is to be discarded; and a discard part reading the segment stored in the packet buffer in an order from the segment having an older sequence number and discarding the segment that is determined to be discarded.

Abstract: A power-ON-clear circuit has a reset period when the power supply stops temporarily (or instantaneously) and then that power supply is restored. The power-ON-clear circuit 30 of a semiconductor integrated circuit 200 comprises: a capacitor C31 of which one end is connected to the external power-supply voltage Vcc1; an N-channel MOS transistor Q31 of which the drain is connected to the other end of the capacitor C31, the source is connected to the ground potential, and the gate is connected to the external power-supply voltage by way of a resistor R31; and an inverter INV31 that is connected to the connecting point between the capacitor C31 and MOS transistor Q31 in a stage connection, and is connected to the power supply between the internal power-supply voltage Vcc2 and the ground potential.

Abstract: When receiving a write request from a processor, a control unit checks the condition of existence (or the presence/absence) in a cache for information necessary for generation of an updated value of a parity record, receives write data and reports the completion of the write request to the processor. In asynchronism with the write request from the processor, the control unit performs a load process for that information among the information necessary for generation of the updated value of the parity record which may be prepared in asynchronism with the write request from the processor and a write after process for the updated value of the parity record.

Abstract: In a BER monitoring circuit, error cycles of input data are detected by a parity check portion and an error cycle detecting portion, a maximum (average/median) value is detected from among the error cycles by an error cycle memory and an error cycle maximum (average/median) value retrieving portion. The value is converted into a corresponding estimated error rate by a Te-BER conversion table and an alarm is generated by an SF/SD detecting -portion when the estimated error rate exceeds an alarm detecting threshold. Thereafter, the alarm is released when the estimated error rate assumes equal to or less than an alarm releasing threshold. Also, an error-free detecting portion is activated when an alarm is generated and releases the alarm when a time period for which the error cycles stay flat exceeds a cycle corresponding to the alarm releasing threshold.

Abstract: A storage system stores multiple copies of data on physical storage implemented, for example, with multiple disk units. Input/output read requests are received from host systems and distributed in a manner that allows parallel read operations to be conducted over the multiple disk units of the physical storage.

Abstract: A method of respectively reading and writing data to and from a plurality of physical disk units in response to I/O requests from a host computing system includes establishing a logical disk group having a number of logical disk elements, mapping each of the logical disk elements to corresponding physical disk units, receiving from the host computing system an I/O request for data to select a one of the number of logical disk elements, accessing the physical disk unit corresponding to the selected one logical disk to access for the data, and transferring the accessed data to the host computing system.

Abstract: In an information processing system having a data processing apparatus, a control unit for a cache memory, and a storage unit for storing a record, respectively interconnected together, wherein when the control unit receives from the data processing apparatus a write request for a record to be written and if the record to be written is not being stored in the cache memory, the control unit receives a data to be written in the object record from the data processing apparatus and stores the received data in the cache memory. After notifying the data processing apparatus of a completion of a data write process, the control unit checks if the object record in which the data stored in the cache memory is being stored in the storage unit, if the object record is being stored in the storage unit, the data in the cache memory is written in the storage unit, and if not, the data in the cache memory is not written and such effect is notified to the data processing apparatus.

Abstract: A power-ON-clear circuit has a reset period when the power supply stops temporarily (or instantaneously) and then that power supply is restored. The power-ON-clear circuit 30 of a semiconductor integrated circuit 200 comprises: a capacitor C31 of which one end is connected to the external power-supply voltage Vcc1; an N-channel MOS transistor Q31 of which the drain is connected to the other end of the capacitor C31, the source is connected to the ground potential, and the gate is connected to the external power-supply voltage by way of a resistor R31; and an inverter INV31 that is connected to the connecting point between the capacitor C31 and MOS transistor Q31 in a stage connection, and is connected to the power supply between the internal power-supply voltage Vcc2 and the ground potential.

Abstract: The control unit arbitrarily with respect to the CPU, including according to an algorithm that is independent of the request a disk unit among the disk units that are inactive when the control unit receives an input/output request involving either read or staging. For a write request from the CPU, the control unit selects a specific disk unit in the disk unit group for the immediate writing of data. In the second kind of load distribution a disk unit is selected to execute read and staging other than the above-mentioned specific disk.