Abstract: SiC is a very stable substance, and it is difficult to control the condition of a SiC surface to be suitable for crystal growth in conventional Group III nitride crystal growing apparatuses. This problem is solved as follows. The surface of a SiC substrate 1 is rendered into a step-terrace structure by performing a heating process in an atmosphere of HCl gas. The surface of the SiC substrate 1 is then treated sequentially with aqua regia, hydrochloric acid, and hydrofluoric acid. A small amount of silicon oxide film formed on the surface of the SiC substrate 1 is etched so as to form a clean SiC surface 3 on the substrate surface. The SiC substrate 1 is then installed in a high-vacuum apparatus and the pressure inside is maintained at ultrahigh vacuum (such as 10?6 to 10?8 Pa). In the ultrahigh vacuum state, a process of irradiating the surface with a Ga atomic beam 5 at time t1 at temperature of 800° C. or lower and performing a heating treatment at 800° C. or higher is repeated at least once.

Abstract: An object of this invention is to provide a band distribution inspecting device and band distribution inspecting method capable of carrying out inspection on whether or not a scattered oscillation signal oscillated containing a frequency variation from the fundamental frequency with the fundamental frequency as a reference point has a band distribution rapidly, with a simple way and at a cheap price. A scattered oscillation signal SSS inputted to a band distribution detecting section 22 is outputted as a predetermined band pass signal SBP through a band pass filter 17 having a predetermined pass band of a predetermined narrow-band width ?f within a band distribution. This signal is converted to a root-mean-square value by a smoother 19, smoothed by a capacitor C1 and transferred to a general purpose inspecting device 21 as a DC signal SAV.

Abstract: A lateral JFET has a basic structure including an n-type semiconductor layer (3) formed of an n-type impurity region and a p-type semiconductor layer formed of a p-type impurity region on the n-type semiconductor layer (3). Moreover, in the p-type semiconductor layer, there are provided a p+-type gate region layer (7) extending into the n-type semiconductor layer (3) and containing p-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3) and an n+-type drain region layer (9) spaced from the p+-type gate region layer (7) by a predetermined distance and containing n-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3). With this structure, the lateral JFET can be provided that has an ON resistance further decreased while maintaining a high breakdown voltage performance.

Abstract: On an SiC single crystal substrate, an electric field relaxation layer and a p? type buffer layer are formed. The electric field relaxation layer is formed between the p? type buffer layer and the SiC single crystal substrate to contact SiC single crystal substrate. On the p? type buffer layer, an n type semiconductor layer is formed. On the n type semiconductor layer, a p type semiconductor layer is formed. In the p type semiconductor layer, an n+ type source region layer and an n+ type drain region layer are formed separated by a prescribed distance from each other. At a part of the region of p type semiconductor layer between the n+ type source region layer and the n+ type drain region layer, a p+ type gate region layer is formed.

Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

Abstract: Disclosed are a diboride single crystal substrate which has a cleavage plane as same as that of a nitride compound semiconductor and is electrically conductive; a semiconductor laser diode and a semiconductor device using such a substrate and methods of their manufacture wherein the substrate is a single crystal substrate 1 of diboride XB2 (where X is either Zr or Ti) which is facially oriented in a (0001) plane 2 and has a thickness of 0.1 mm or less. The substrate 1 is permitted cleaving and splitting along a (10-10) plane 4 with ease. Using this substrate to form a semiconductor laser diode of a nitride compound, a vertical structure device can be realized. Resonant planes of a semiconductor laser diode with a minimum of loss can be fabricated by splitting the device in a direction parallel to the (10-10) plane. A method of manufacture that eliminates a margin of cutting is also realized.

Abstract: A lateral JFET has a basic structure including an n-type semiconductor layer (3) formed of an n-type impurity region and a p-type semiconductor layer formed of a p-type impurity region on the n-type semiconductor layer (3). Moreover, in the p-type semiconductor layer, there are provided a p+-type gate region layer (7) extending into the n-type semiconductor layer (3) and containing p-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3) and an n+-type drain region layer (9) spaced from the p+-type gate region layer (7) by a predetermined distance and containing n-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3). With this structure, the lateral JFET can be provided that has an ON resistance further decreased while maintaining a high breakdown voltage performance.

Abstract: A charge pump circuit is disclosed in which a spike-shaped noise (glitch) generated in an output is reduced. The charge pump circuit comprises: a first transistor, one of the terminals of which is connected to a high electric potential power source, turned on and off according to a charge-up signal; a second transistor, one of the terminals of which is connected to a low electric potential power source, turned on and off according to a charge-down signal; a first current restricting element connected between the other terminal of the first transistor and the output of a charge pump; and a second current restricting element connected between the other terminal of the second transistor and the output of the charge pump.

Abstract: To present a clock generator capable of spreading the spectrum of oscillation frequency by simple control in a small additional circuit, and its control method. A phase locked loop circuit is provided from a frequency phase comparator 11, an output clock signal PO is outputted from a voltage control oscillator (VCO) 14 by way of a charge pump circuit (CP) 12 and a loop filter (LF) 13, and is returned to the frequency phase comparator 11 by way of a frequency divider (DIV) 15. Detecting the phase difference of reference clock signal R and divided clock signal D, and locking the oscillation frequency of the output clock signal PO to specified frequency, a modulation signal M is outputted from a modulation pulse generator 1 regardless of phase locked control of phase locked loop circuit, and is superposed on phase comparison signal P, and thereby the oscillation frequency of output clock signal PO is modulated. An output clock signal PO having a predetermined spectrum spread characteristic can be obtained.

Abstract: A method for manufacturing a silicon carbide semiconductor device includes the steps of: forming a trench mask on an upper surface of a semiconductor substrate; forming the trench such that the trench having an aspect ratio equal to or larger than 2 and having a trench slanting angle equal to or larger than 80 degrees is formed; and removing a damage portion in such a manner that the damage portion disposed on an inner surface of the trench formed in the semiconductor substrate in the step of forming the trench is etched and removed in hydrogen atmosphere under decompression pressure at a temperature equal to or higher than 1600° C.

Abstract: 4H-InGaAlN alloy based optoelectronic and electronic devices on non-polar face are formed on 4H-AlN or 4H-AlGaN on (11-20) a-face 4H-SiC substrates. Typically, non polar 4H-AlN is grown on 4H-SiC (11-20) by molecular beam epitaxy (MBE). Subsequently, III-V nitride device layers are grown by metal organic chemical vapor deposition (MOCVD) with 4H-polytype for all of the layers. The non-polar device does not contain any built-in electric field due to the spontaneous and piezoelectric polarization. The optoelectonic devices on the non-polar face exhibits higher emission efficiency with shorter emission wavelength because the electrons and holes are not spatially separated in the quantum well. Vertical device configuration for lasers and light emitting diodes(LEDs) using conductive 4H-AlGaN interlayer on conductive 4H-SiC substrates makes the chip size and series resistance smaller. The elimination of such electric field also improves the performance of high speed and high power transistors.

Abstract: A lateral junction field effect transistor includes a first gate electrode layer (18A) arranged in a third semiconductor layer (13) between source/drain region layers (6, 8), having a lower surface extending on the second semiconductor layer (12), and doped with p-type impurities more heavily than the second semiconductor layer (12), and a second gate electrode layer (18B) arranged in a fifth semiconductor layer (15) between the source/drain region layers (6, 8), having a lower surface extending on a fourth semiconductor layer (14), having substantially the same concentration of p-type impurities as the first gate electrode layer (18A), and having the same potential as the first gate electrode layer (18A). Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

Abstract: A junction field effect transistor (JFET) is provided that is capable of a high voltage resistance, high current switching operation, that operates with a low loss, and that has little variation. This JFET is provided with a gate region (2) of a second conductivity type provided on a surface of a semiconductor substrate, a source region (1) of a first conductivity type, a channel region (10) of the first conductivity type that adjoins the source region, a confining region (5) of the second conductivity type that adjoins the gate region and confines the channel region, a drain region (3) of the first conductivity type provided on a reverse face, and a drift region (4) of the first conductivity type that continuously lies in a direction of thickness of the substrate from a channel to a drain.

Abstract: An object of this invention is to provide a band distribution inspecting device and band distribution inspecting method capable of carrying out inspection on whether or not a scattered oscillation signal oscillated containing a frequency variation from the fundamental frequency with the fundamental frequency as a reference point has a band distribution rapidly, with a simple way and at a cheap price. A scattered oscillation signal SSS inputted to a band distribution detecting section 22 is outputted as a predetermined band pass signal SBP through a band pass filter 17 having a predetermined pass band of a predetermined narrow-band width ?f within a band distribution. This signal is converted to a root-mean-square value by a smoother 19, smoothed by a capacitor C1 and transferred to a general purpose inspecting device 21 as a DC signal SAV.

Abstract: A silicon carbide (SiC) substrate is provided with an off-oriented {0001} surface whose off-axis direction is <11-20>. A trench is formed on the SiC to have a stripe structure extending toward a <11-20> direction. An SiC epitaxial layer is formed on an inside surface of the trench.

Abstract: A SiC wafer comprises a 4H polytype SiC substrate 2 in which the crystal plane orientation is substantially {03-38}, and a buffer layer 4 composed of SiC formed over this SiC substrate 2. The {03-38} plane forms an angle of approximately 35° with respect to the <0001> axial direction in which micropipes and so forth extend, so micropipes and so forth are eliminated at the crystal sides, and do not go through to an active layer 6 on the buffer layer 4. Lattice mismatching between the SiC substrate 2 and the active layer 6 is suppressed by the buffer layer 4. Furthermore, anisotropy in the electron mobility is low because a 4H polytype is used. Therefore, it is possible to obtain a SiC wafer and a SiC semiconductor device with which there is little anisotropy in the electron mobility, and strain caused by lattice mismatching can be lessened, as well as a method for manufacturing these.

Abstract: A silicon carbide (SiC) substrate is provided with an off-oriented {0001} surface whose off-axis direction is <11-20>. A trench is formed on the SiC to have a stripe structure extending toward a <11-20> direction. An SiC epitaxial layer is formed on an inside surface of the trench.

Abstract: A method of growing a 4H-poly type SiC single crystal 40, characterized in that the 4H-poly type SiC single crystal 40 is grown on a seed crystal 30 comprised of an SiC single crystal where a {03-38} plane 30u or a plane which is inclined at off angle &agr;, within about 10°, with respect to the {03-38} plane, is exposed.

Abstract: A lateral JFET has a basic structure including an n-type semiconductor layer (3) formed of an n-type impurity region and a p-type semiconductor layer formed of a p-type impurity region on the n-type semiconductor layer (3). Moreover, in the p-type semiconductor layer, there are provided a p+-type gate region layer (7) extending into the n-type semiconductor layer (3) and containing p-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3) and an n+-type drain region layer (9) spaced from the p+-type gate region layer (7) by a predetermined distance and containing n-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3). With this structure, the lateral JFET can be provided that has an ON resistance further decreased while maintaining a high breakdown voltage performance.

Abstract: A Digital/Analog converter comprising a plurality of current sources, and a selecting circuit for selecting a current source from the plurality of current sources on the basis of a digital signal. The selecting circuit includes a first transistor in which the digital signal is supplied. The selecting circuit also includes a second transistor with the same conductivity type as the first transistor for receiving an inverted digital signal of the digital signal. The second transistor is connected to the output of the first transistor.