Patents by Inventor Hiroyuki Miyake

Hiroyuki Miyake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230012554
    Abstract: A display device in which parasitic capacitance between wirings can be reduced is provided. Furthermore, a display device in which display quality is improved is provided. Furthermore, a display device in which power consumption can be reduced is provided. The display device includes a signal line, a scan line, a first electrode, a second electrode, a third electrode, a first pixel electrode, a second pixel electrode, and a semiconductor film.
    Type: Application
    Filed: September 21, 2022
    Publication date: January 19, 2023
    Inventors: Hiroyuki MIYAKE, Makoto KANEYASU
  • Patent number: 11552107
    Abstract: Provided is a display device with extremely high resolution, a display device with higher display quality, a display device with improved viewing angle characteristics, or a flexible display device. Same-color subpixels are arranged in a zigzag pattern in a predetermined direction. In other words, when attention is paid to a subpixel, another two subpixels exhibiting the same color as the subpixel are preferably located upper right and lower right or upper left and lower left. Each pixel includes three subpixels arranged in an L shape. In addition, two pixels are combined so that pixel units including subpixel are arranged in matrix of 3×2.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: January 10, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisao Ikeda, Kouhei Toyotaka, Hideaki Shishido, Hiroyuki Miyake, Kohei Yokoyama, Yasuhiro Jinbo, Yoshitaka Dozen, Takaaki Nagata, Shinichi Hirasa
  • Publication number: 20220415893
    Abstract: It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.
    Type: Application
    Filed: August 19, 2022
    Publication date: December 29, 2022
    Inventors: Yutaka SHIONOIRI, Hiroyuki MIYAKE, Kiyoshi KATO
  • Patent number: 11535155
    Abstract: Superimposed-image display devices and programs display a guide image providing a guidance of information to a driver of a vehicle such that the guide image is superimposed on a view ahead of the vehicle and is visually recognized. The systems and programs obtain three-dimensional map information that specifies a three-dimensional shape of a road and a structure nearby the road and arrange the guide image in the three-dimensional map information, based on the three-dimensional shape of the road and the structure nearby the road. The systems and programs obtain a shape of the guide image that is visually recognized from a position of the driver in the three-dimensional map information and display the guide image having the obtained shape.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: December 27, 2022
    Assignee: AISIN CORPORATION
    Inventors: Kenji Watanabe, Hiroyuki Miyake, Yuusuke Morita
  • Patent number: 11525694
    Abstract: Superimposed-image display devices and programs superimpose an image on a surrounding environment in front of a vehicle so that the image can be visually identified. The image includes at least one of a first guidance image that prompts a driver to change driving operation and a second guidance image that does not prompt a driver to change driving operation. The second guidance image is displayed in a display mode in which the second guidance image more harmonizes in at least one of a location, brightness, and color with the surrounding environment than the first guidance image, the surrounding environment being a superimposition target.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: December 13, 2022
    Assignee: AISIN CORPORATION
    Inventors: Kenji Watanabe, Hiroyuki Miyake
  • Patent number: 11511627
    Abstract: Display devices and programs display a guide image on a display mounted on a vehicle so as to be visually recognized such that the guide image is superimposed on a view ahead of the vehicle. The guide image provides guidance about a travel direction of the vehicle that travels on a travel path after leaving a guide branch point. The devices and programs display the guide image in a manner such that a region overlapping a nearby object present on a near side of the travel path on which the vehicle travels is removed from the guide image.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: November 29, 2022
    Assignee: AISIN CORPORATION
    Inventors: Kenji Watanabe, Hiroyuki Miyake, Josaku Nakanishi
  • Patent number: 11493808
    Abstract: A display device in which parasitic capacitance between wirings can be reduced is provided. Furthermore, a display device in which display quality is improved is provided. Furthermore, a display device in which power consumption can be reduced is provided. The display device includes a signal line, a scan line, a first electrode, a second electrode, a third electrode, a first pixel electrode, a second pixel electrode, and a semiconductor film.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: November 8, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroyuki Miyake, Makoto Kaneyasu
  • Patent number: 11493357
    Abstract: A guide object for proposing a guide target point is displayed when there is a guide target point that is to be proposed, ahead of a vehicle in a traveling direction. In contrast, when displaying the guide object, the guide object is displayed in a form in which an occupant visually recognizes the guide object with a relative position of the guide object with respect to the vehicle fixed, when a distance from the vehicle to the guide target point is equal to or more than a threshold. Further, the guide object is displayed in a form in which the occupant visually recognizes the guide object as being superimposed with a relative position of the guide object with respect to the guide target point fixed, when the distance from the vehicle to the guide target point is less than the threshold.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: November 8, 2022
    Assignee: AISIN CORPORATION
    Inventors: Takashi Kawai, Toshinori Takeuchi, Kenji Watanabe, Hiroyuki Miyake
  • Publication number: 20220328529
    Abstract: To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor, a clock signal is input to a gate electrode of the first switching transistor, and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.
    Type: Application
    Filed: January 14, 2022
    Publication date: October 13, 2022
    Inventors: Atsushi UMEZAKI, Hiroyuki MIYAKE
  • Patent number: 11468860
    Abstract: In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a batch mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: October 11, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Seiko Amano, Hiroyuki Miyake
  • Patent number: 11460737
    Abstract: A display device with less light leakage and excellent contrast is provided. A display device having a high aperture ratio and including a large-capacitance capacitor is provided. A display device in which wiring delay due to parasitic capacitance is reduced is provided. A display device includes a transistor over a substrate, a pixel electrode connected to the transistor, a signal line electrically connected to the transistor, a scan line electrically connected to the transistor and intersecting with the signal line, and a common electrode overlapping with the pixel electrode and the signal line with an insulating film provided therebetween. The common electrode includes stripe regions extending in a direction intersecting with the signal line.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: October 4, 2022
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Ryo Hatsumi, Daisuke Kubota, Hiroyuki Miyake
  • Publication number: 20220284976
    Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L, of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.
    Type: Application
    Filed: May 20, 2022
    Publication date: September 8, 2022
    Inventors: Seiko AMANO, Kouhei TOYOTAKA, Hiroyuki MIYAKE, Aya MIYAZAKI, Hideaki SHISHIDO, Koji KUSUNOKI
  • Publication number: 20220278680
    Abstract: An object of the present invention is to suppress deterioration in the thin film transistor. A plurality of pulse output circuits each include first to eleventh thin film transistors is formed. The pulse output circuit is operated on the basis of a plurality of clock signals which control each transistor, the previous stage signal input from a pulse output circuit in the previous stage, the next stage signal input from a pulse output circuit in the next stage, and a reset signal. In addition, a microcrystalline semiconductor is used for a semiconductor layer serving as a channel region of each transistor. Therefore, degradation of characteristics of the transistor can be suppressed.
    Type: Application
    Filed: May 12, 2022
    Publication date: September 1, 2022
    Inventors: Hiroyuki MIYAKE, Kei TAKAHASHI
  • Patent number: 11424246
    Abstract: It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: August 23, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Hiroyuki Miyake, Kiyoshi Kato
  • Patent number: 11404447
    Abstract: A display device including a display portion with an extremely high resolution is provided. The display device includes a pixel circuit and a light-emitting element. The pixel circuit includes a first element layer including a first transistor and a second element layer including a second transistor. A channel formation region of the first transistor includes silicon. The first transistor has a function of driving the light-emitting element. The second transistor functions as a switch. A channel formation region of the second transistor includes a metal oxide. The metal oxide functions as a semiconductor. The second element layer is provided over the first element layer.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: August 2, 2022
    Inventors: Kei Takahashi, Hiroyuki Miyake
  • Publication number: 20220236824
    Abstract: A circuit which detects an output current from a pixel and an output current from an input device, and converts the output current into data is provided. The current detection circuit includes an integer circuit, a comparator, a counter, and a latch. The integrator circuit integrates the potential of a first signal during a period determined by a second signal and outputting it as a third signal. The comparator compares the potential of the third signal with a first potential and outputting a fourth signal. The counter outputs the number of pulses included in a fifth signal as a sixth signal during a period determined by the fourth signal. The latch holds the sixth signal. The integrator circuit preferably further includes an operational amplifier and some capacitors. The first signal is supplied from a pixel included in a display device or an input portion included in an input device.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Inventors: Kei TAKAHASHI, Hiroyuki MIYAKE
  • Publication number: 20220215810
    Abstract: To provide a semiconductor device including a narrowed bezel obtained by designing a gate driver circuit. A gate driver of a display device includes a shift register unit, a demultiplexer circuit, and n signal lines. By connecting the n signal lines for transmitting clock signals to one stage of the shift register unit, (n-3) output signals can be output. The larger n becomes, the smaller the rate of signal lines for transmitting clock signals which do not contribute to output becomes; accordingly, the area of the shift register unit part is small compared to a conventional structure in which one stage of a shift register unit outputs one output signal. Therefore, the gate driver circuit can have a narrow bezel.
    Type: Application
    Filed: March 23, 2022
    Publication date: July 7, 2022
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroyuki Miyake, Kouhei TOYOTAKA, Shunpei YAMAZAKI
  • Publication number: 20220173131
    Abstract: A display device including a display portion with an extremely high resolution is provided. The display device includes a pixel circuit and a light-emitting element. The pixel circuit includes a first element layer including a first transistor and a second element layer including a second transistor. A channel formation region of the first transistor includes silicon. The first transistor has a function of driving the light-emitting element. The second transistor functions as a switch. A channel formation region of the second transistor includes a metal oxide. The metal oxide functions as a semiconductor. The second element layer is provided over the first element layer.
    Type: Application
    Filed: February 16, 2022
    Publication date: June 2, 2022
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kei Takahashi, Hiroyuki Miyake
  • Patent number: 11348653
    Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: May 31, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Seiko Amano, Kouhei Toyotaka, Hiroyuki Miyake, Aya Miyazaki, Hideaki Shishido, Koji Kusunoki
  • Publication number: 20220165758
    Abstract: An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.
    Type: Application
    Filed: February 8, 2022
    Publication date: May 26, 2022
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Hiroyuki MIYAKE