Patents by Inventor Hiroyuki Ohta

Hiroyuki Ohta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus for measuring a mechanical quantity
    Patent number: 7707894
    Abstract: An apparatus structure and measurement method are provided to retain high precision and high reliability of a semiconductor mechanical quantity measuring apparatus which senses a mechanical quantity and transmits measured information wirelessly. As to a silicon substrate of the semiconductor mechanical quantity measuring apparatus, for example, a ratio of a substrate thickness to a substrate length along a measurement direction is set small, and a ratio of a substrate thickness to a substrate length along a direction perpendicular to the measurement direction is set small. The apparatus upper surface is covered with a protective member. It is possible to measure a strain along a particular direction and realize mechanical quantity measurement with less error and high precision. An impact resistance and environment resistance of the apparatus itself can be improved.
    Type: Grant
    Filed: September 15, 2008
    Date of Patent: May 4, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Sumigawa, Hiroyuki Ohta
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
    Publication number: 20100078729
    Abstract: A semiconductor device includes a transistor configuration including first and second gate electrodes, each of the first and second gate electrodes having at least a bottom layer and an upper layer including polycrystalline silicon grains, wherein the first gate electrode is a nMOS gate electrode formed in an nMOS region of the transistor configuration, wherein the polycrystalline silicon grains included in the bottom layer of the first gate electrode have a greater particle diameter than the polycrystalline grains included in the upper layer of the second gate electrode.
    Type: Application
    Filed: September 25, 2009
    Publication date: April 1, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Hidenobu Fukutome, Hiroyuki Ohta, Mitsugu Tajima
  • Semiconductor device and production method thereof
    Patent number: 7683362
    Abstract: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: March 23, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Hiroyuki Ohta, Takashi Sakuma, Yosuke Shimamune, Akiyoshi Hatada, Akira Katakami, Naoyoshi Tamura
  • Semiconductor device, and method and apparatus for manufacturing the same
    Patent number: 7678711
    Abstract: A SiO2 film is formed on a semiconductor substrate. Then, a SiN film is formed on the SiO2 film. In this event bis(tertiary butyl amino) silane and NH3 are used as a material gas, and the film forming temperature is set to 600° C. or lower.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: March 16, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Mitsuaki Hori, Hiroyuki Ohta, Katsuaki Ookoshi
  • Semiconductor device and fabrication process thereof
    Patent number: 7678641
    Abstract: There is provided a semiconductor device having a device isolation region of STI structure formed on a silicon substrate so as to define a device region, wherein the device isolation region comprises a device isolation trench formed in the silicon substrate, and a device isolation insulation film filling the device isolation trench. At least a surface part of the device isolation insulation film is formed of an HF-resistant film.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: March 16, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Toshifumi Mori, Katsuaki Ookoshi, Takashi Watanabe, Hiroyuki Ohta
  • Semiconductor device and method of fabricating the same
    Patent number: 7663187
    Abstract: An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a semiconductor substrate within a surficial layer thereof and in alignment with the first sidewall spacer, to thereby form an amorphous diffusion suppressive region.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: February 16, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Takashi Saiki, Hiroyuki Ohta, Hiroyuki Kanata
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20100015774
    Abstract: A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.
    Type: Application
    Filed: September 22, 2009
    Publication date: January 21, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Yosuke SHIMAMUNE, Masahiro Fukuda, Young Suk Kim, Akira Katakami, Akiyoshi Hatada, Naoyoshi Tamura, Hiroyuki Ohta
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20100003798
    Abstract: A semiconductor device comprises a field-effect transistor arranged in a semiconductor substrate, which transistor has a gate electrode, source/drain impurity diffusion regions, and carbon layers surrounding the source/drain impurity diffusion regions. Each of the carbon layers is provided at an associated of the source/drain impurity diffusion regions and positioned so as to be offset from the front edge of a source/drain extension in direction away from the gate electrode and to surround as profile the associated source/drain impurity diffusion region.
    Type: Application
    Filed: August 31, 2009
    Publication date: January 7, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Hiroyuki OHTA, Kenichi OKABE
  • Semiconductor Device
    Publication number: 20090321783
    Abstract: A semiconductor device which includes a semiconductor chip; an electrically conductive base electrode bonded to the lower surface of the semiconductor chip by a first bonding member; an electrically conductive lead electrode bonded to the upper surface of the semiconductor chip by a second bonding member; and a first stress relief member for reducing stress developed in the first bonding member due to the difference in thermal expansion between the semiconductor chip and the base electrode, wherein both the base electrode and the first stress relief member are in direct contact with the lower surface of the first bonding member.
    Type: Application
    Filed: June 29, 2009
    Publication date: December 31, 2009
    Inventors: Shinji Hiramitsu, Hiroyuki Ohta, Koji Sasaki, Masato Nakamura, Osamu Ikeda, Satoshi Matsuyoshi
  • METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING EPITAXIALLY GROWING SEMICONDUCTOR EPITAXIAL LAYERS ON A SURFACE OF SEMICONDUCTOR SUBSTRATE
    Publication number: 20090302395
    Abstract: A semiconductor device has a first MOS transistor formed on first active region of the first conductivity type, having first gate electrode structure, first source/drain regions, recesses formed in the first source/drain regions, and semiconductor buried regions buried and grown on the recesses for applying stress to the channel under the first gate electrode structure, and a second MOS transistor formed on second active region of the second conductivity type, having second gate electrode structure, second source/drain regions, and semiconductor epitaxial layers formed on the second source/drain regions without forming recesses and preferably applying stress to the channel under the second gate electrode structure. In a CMOS device, performance can be improved by utilizing stress and manufacture processes can be simplified.
    Type: Application
    Filed: August 14, 2009
    Publication date: December 10, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Hiroyuki OHTA
  • Semiconductor device and method of manufacturing the same
    Patent number: 7626215
    Abstract: A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: December 1, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Yosuke Shimamune, Masahiro Fukuda, Young Suk Kim, Akira Katakami, Akiyoshi Hatada, Naoyoshi Tamura, Hiroyuki Ohta
  • Semiconductor device and production method thereof
    Publication number: 20090280612
    Abstract: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.
    Type: Application
    Filed: July 17, 2009
    Publication date: November 12, 2009
    Applicant: Fujitsu Microelectronics Limited
    Inventors: Yosuke Shimamune, Hiroyuki Ohta, Akiyoshi Hatada, Akira Katakami, Naoyoshi Tamura
  • Semiconductor device and manufacturing method thereof
    Patent number: 7601996
    Abstract: A semiconductor device comprises a field-effect transistor arranged in a semiconductor substrate, which transistor has a gate electrode, source/drain impurity diffusion regions, and carbon layers surrounding the source/drain impurity diffusion regions. Each of the carbon layers is provided at an associated of the source/drain impurity diffusion regions and positioned so as to be offset from the front edge of a source/drain extension in direction away from the gate electrode and to surround as profile the associated source/drain impurity diffusion region.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: October 13, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Hiroyuki Ohta, Kenichi Okabe
  • Method of manufacturing a semiconductor device including epitaxially growing semiconductor epitaxial layers on a surface of semiconductor substrate
    Patent number: 7592214
    Abstract: A semiconductor device has a first MOS transistor formed on first active region of the first conductivity type, having first gate electrode structure, first source/drain regions, recesses formed in the first source/drain regions, and semiconductor buried regions buried and grown on the recesses for applying stress to the channel under the first gate electrode structure, and a second MOS transistor formed on second active region of the second conductivity type, having second gate electrode structure, second source/drain regions, and semiconductor epitaxial layers formed on the second source/drain regions without forming recesses and preferably applying stress to the channel under the second gate electrode structure. In a CMOS device, performance can be improved by utilizing stress and manufacture processes can be simplified.
    Type: Grant
    Filed: May 2, 2007
    Date of Patent: September 22, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Hiroyuki Ohta
  • Semiconductor device with STI and its manufacture
    Patent number: 7589391
    Abstract: A semiconductor device includes: a silicon substrate with semiconductor elements; an isolation trench formed in the silicon substrate for isolating active regions in the silicon substrate, the isolation trench having a trapezoidal cross sectional shape having a width gradually narrowing with a depth from the surface of the silicon substrate; a first liner insulating film formed on the surface of the trench and made of a silicon oxide film or a silicon oxynitride film having a thickness of 1 to 5 nm; a second liner insulating film formed on the first liner insulating film and made of a silicon nitride film having a thickness of 2 to 8 nm; and an isolation region burying the trench defined by the second liner insulating film.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: September 15, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Hiroyuki Ohta, Yasunori Iriyama
  • Semiconductor device and method of fabricating the same
    Patent number: 7585739
    Abstract: An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a semiconductor substrate within a surficial layer thereof and in alignment with the first sidewall spacer, to thereby form an amorphous diffusion suppressive region.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: September 8, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Takashi Saiki, Hiroyuki Ohta, Hiroyuki Kanata
  • Monitoring system for valve device
    Patent number: 7584668
    Abstract: A monitoring system for valve device according to the present invention comprises a semiconductor single crystalline substrate including a bridged circuit and the bridged circuit comprising impurity-diffused resistors. The semiconductor single crystalline substrate is mounted to any of a valve device's valve stem, valve yoke, drive shaft, or elastic body disposed at the end of the drive shaft. Thrust and torque of the valve device are measured by the semiconductor single crystalline substrate and then the measured values are used for monitoring the valve device.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: September 8, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Ohta, Hiromi Shimazu, Yohei Tanno, Yoshihisa Kiyotoki, Kenji Onodera, Kenji Araki
  • SEMICONDUCTOR DEVICE
    Publication number: 20090212437
    Abstract: In a semiconductor device having a Low-k film as an interlayer insulator, peeling of the interlayer insulator in a thermal cycle test is prevented, thereby providing a highly reliable semiconductor device. In a semiconductor device having a structure in which interlayer insulators in which buried wires each having a main electric conductive layer made of copper are formed and cap insulators of the buried wires are stacked, the cap insulator having a relatively high Young's modulus and contacting by its upper surface with the interlayer insulator made of a Low-k film having a relatively low Young's modulus is formed so as not to be provided in an edge portion of the semiconductor device.
    Type: Application
    Filed: February 19, 2009
    Publication date: August 27, 2009
    Inventors: Yukihiro Kumagai, Hiroyuki Ohta, Naotaka Tanaka, Masahiko Fujisawa, Akihiko Ohsaki
  • Digital camera
    Patent number: D610182
    Type: Grant
    Filed: February 12, 2009
    Date of Patent: February 16, 2010
    Assignee: Olympus Imaging Corp.
    Inventor: Hiroyuki Ohta
  • Digital camera
    Patent number: D611083
    Type: Grant
    Filed: February 12, 2009
    Date of Patent: March 2, 2010
    Assignee: Olympus Imaging Corp.
    Inventor: Hiroyuki Ohta