Patents by Inventor Hisao Miyazaki

Hisao Miyazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190259707
    Abstract: A graphene wiring structure of an embodiment has: an amorphous or polycrystalline insulating film; and a multilayer graphene on the insulating film. The multilayer graphene including a plurality of graphene crystals having a zigzag direction is oriented at 17 degrees or less with respect to an electric conduction direction on the insulating film.
    Type: Application
    Filed: April 30, 2019
    Publication date: August 22, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hisao MIYAZAKI, Tadashi Sakai, Yasutaka Nishida, Takashi Yoshida, Yuichi Yamazaki, Masayuki Katagiri, Naoshi Sakuma
  • Patent number: 10325851
    Abstract: A graphene wiring structure of an embodiment has: an amorphous or polycrystalline insulating film; and a multilayer graphene on the insulating film. The multilayer graphene including a plurality of graphene crystals having a zigzag direction is oriented at 17 degrees or less with respect to an electric conduction direction on the insulating film.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: June 18, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisao Miyazaki, Tadashi Sakai, Yasutaka Nishida, Takashi Yoshida, Yuichi Yamazaki, Masayuki Katagiri, Naoshi Sakuma
  • Publication number: 20180277487
    Abstract: A graphene wiring structure of an embodiment has: an amorphous or polycrystalline insulating film; and a multilayer graphene on the insulating film. The multilayer graphene including a plurality of graphene crystals having a zigzag direction is oriented at 17 degrees or less with respect to an electric conduction direction on the insulating film.
    Type: Application
    Filed: August 30, 2017
    Publication date: September 27, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hisao MIYAZAKI, Tadashi SAKAI, Yasutaka NISHIDA, Takashi YOSHIDA, Yuichi YAMAZAKI, Masayuki KATAGIRI, Naoshi SAKUMA
  • Publication number: 20180269157
    Abstract: A wiring of an embodiment includes: a multilayer graphene including graphene sheets laminated in a first direction, the multilayer graphene extended in a second direction regarded as a longitudinal direction that intersects with the first direction; a first metal part in direct contact with the multilayer graphene; a second metal part spaced apart from the first metal part in the second direction, the second metal part in direct contact with the multilayer graphene; a first conductive part disposed on the multilayer graphene in the first direction, and electrically connected to the multilayer graphene with the first metal part interposed therebetween; and a second conductive part disposed on the multilayer graphene in the first direction, and electrically connected to the multilayer graphene with the second metal part interposed therebetween.
    Type: Application
    Filed: September 1, 2017
    Publication date: September 20, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki KATAGIRI, Tatsuro SAITO, Tadashi SAKAI, Hisao MIYAZAKI
  • Patent number: 9997611
    Abstract: A graphene wiring structure of an embodiment has a multilayered graphene having a plurality of planar graphene sheets laminated, and a first interlayer substance being a metal oxyhalide between the plurality of planar graphene sheets.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: June 12, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisao Miyazaki, Tadashi Sakai, Masayuki Katagiri, Yuichi Yamazaki
  • Patent number: 9924593
    Abstract: A graphene wiring structure of an embodiment has a substrate, a metal part on the substrate, multilayered graphene connected to the metal part, a first insulative film on the substrate, and a second insulative film on the substrate. The metal part is present between the first insulative film and the second insulative film. Edges of the multilayered graphene are connected to the metal part. A side face of the first insulative film vertical to the substrate opposes a side face of the second insulative film vertical to the substrate. A first outer face of the multilayered graphene is in physical contact with a first side face of the first insulative film vertical to the substrate. A second outer face of the multilayered graphene is in physical contact with a second side face of the second insulative film vertical to the substrate.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: March 20, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadashi Sakai, Yuichi Yamazaki, Hisao Miyazaki, Masayuki Katagiri, Taishi Ishikura, Akihiro Kajita
  • Publication number: 20180012846
    Abstract: A graphene structure of an embodiment includes multilayer graphene laminated with graphene sheets, and a first interlayer material being present between the graphene sheets of the multilayer graphene and containing a multimer of molybdenum oxide.
    Type: Application
    Filed: March 1, 2017
    Publication date: January 11, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hisao MIYAZAKI, Takashi YOSHIDA, Masayuki KATAGIRI, Yuichi YAMAZAKI, Tadashi SAKAI
  • Patent number: 9768372
    Abstract: A semiconductor device of an embodiment includes a layered substance formed by laminating two-dimensional substances in two or more layers. The layered substance includes at least either one of a p-type region having a first intercalation substance between layers of the layered substance and an n-type region having a second intercalation substance between layers of the layered substance. The layered substance includes a conductive region that is adjacent to at least either one of the p-type region and the n-type region. The conductive region includes neither the first intercalation substance nor the second intercalation substance. A sealing member is formed on the conductive region, or on the conductive region and an end of the layered substance.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: September 19, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisao Miyazaki, Yuichi Yamazaki, Tadashi Sakai
  • Patent number: 9761530
    Abstract: Graphene wiring of an embodiment has a graphene intercalation compound including a multilayer graphene having graphene sheets stacked therein and an interlayer substance disposed between layers of the multilayer graphene, and an interlayer cross-linked layer connected to a side surface of the multilayer graphene. The interlayer cross-linked layer has a cross-linked molecular structure including multiple bonded molecules cross-linking the graphene sheets included in the multilayer graphene.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: September 12, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisao Miyazaki, Tadashi Sakai, Yuichi Yamazaki, Masayuki Katagiri
  • Publication number: 20170256499
    Abstract: A graphene wiring structure of an embodiment has a multilayered graphene having a plurality of planar graphene sheets laminated, and a first interlayer substance being a metal oxyhalide between the plurality of planar graphene sheets.
    Type: Application
    Filed: December 27, 2016
    Publication date: September 7, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hisao MIYAZAKI, Tadashi Sakai, Masayuki Katagiri, Yuichi Yamazaki
  • Patent number: 9679851
    Abstract: A graphene wring structure of an embodiment includes multilayer graphene, a first interlayer compound existing in an interlayer space of the multilayer graphene, and a second interlayer compound existing in the interlayer space of the multilayer graphene. The second interlayer compound containing at least one of an oxide, a nitride and a carbide.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: June 13, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadashi Sakai, Hisao Miyazaki, Masayuki Katagiri, Yuichi Yamazaki
  • Patent number: 9659870
    Abstract: Wiring comprises a multilayer graphene including graphene sheets, an interlayer substance disposed between layers of the multilayer graphene, and an organic compound layer connected to a side surface of the multilayer graphene. The organic compound layer contains a photoisomerizable organic group connected to the multilayer graphene.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: May 23, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisao Miyazaki, Tadashi Sakai
  • Publication number: 20170077178
    Abstract: A nonvolatile storage device of an embodiment includes a first wiring layer extending in a first direction, a second wiring layer extending in a second direction intersecting with the first direction, a conductive layer between the first wiring layer and the second wiring layer at an intersection of the first wiring layer and the second wiring layer, and a resistance change region including at least one of an oxide, a nitride, and an oxynitride in the first wiring layer. The resistance change region exists in the first wiring layer including an interface between the first wiring layer and the conductive layer.
    Type: Application
    Filed: August 30, 2016
    Publication date: March 16, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hisao MIYAZAKI, Tadashi SAKAI, Yuichi YAMAZAKI, Masayuki KATAGIRI
  • Publication number: 20170079138
    Abstract: A graphene wiring structure of an embodiment has a substrate, a metal part on the substrate, multilayered graphene connected to the metal part, a first insulative film on the substrate, and a second insulative film on the substrate. The metal part is present between the first insulative film and the second insulative film. Edges of the multilayered graphene are connected to the metal part. A side face of the first insulative film vertical to the substrate opposes a side face of the second insulative film vertical to the substrate. A first outer face of the multilayered graphene is in physical contact with a first side face of the first insulative film vertical to the substrate. A second outer face of the multilayered graphene is in physical contact with a second side face of the second insulative film vertical to the substrate.
    Type: Application
    Filed: September 1, 2016
    Publication date: March 16, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tadashi SAKAI, Yuichi YAMAZAKI, Hisao MIYAZAKI, Masayuki KATAGIRI, Taishi ISHIKURA, Akihiro KAJITA
  • Publication number: 20160284646
    Abstract: A graphene wring structure of an embodiment includes multilayer graphene, a first interlayer compound existing in an interlayer space of the multilayer graphene, and a second interlayer compound existing in the interlayer space of the multilayer graphene. The second interlayer compound containing at least one of an oxide, a nitride and a carbide.
    Type: Application
    Filed: February 29, 2016
    Publication date: September 29, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tadashi SAKAI, Hisao MIYAZAKI, Masayuki KATAGIRI, Yuichi YAMAZAKI
  • Publication number: 20160276219
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming a graphene film on a catalytic layer, removing a part of the graphene film to form an exposed side surface of the graphene film, introducing dopant into the graphene film from the exposed side surface, and forming a graphene interconnect by patterning the graphene film into which the dopant is introduced.
    Type: Application
    Filed: August 31, 2015
    Publication date: September 22, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto WADA, Yuichi YAMAZAKI, Hisao MIYAZAKI, Akihiro KAJITA, Tatsuro SAITO, Atsunobu ISOBAYASHI, Taishi ISHIKURA, Masayuki KATAGIRI, Tadashi SAKAI
  • Patent number: 9418938
    Abstract: A semiconductor device includes a graphene interconnect, an insulation film formed on the graphene interconnect, and a via conducting portion formed in a via hole provided in the graphene interconnect and the insulation film. The graphene interconnect has a region containing an impurity at least around the via hole.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: August 16, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayuki Kitamura, Atsuko Sakata, Hisao Miyazaki, Akihiro Kajita, Tadashi Sakai
  • Patent number: 9379060
    Abstract: A graphene wiring has a substrate, a catalyst layer on the substrate, a graphene layer on the catalyst layer, and a dopant layer on a side surface of the graphene layer. An atomic or molecular species is intercalated in the graphene layer or disposed on the graphene layer.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: June 28, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisao Miyazaki, Tadashi Sakai, Masayuki Katagiri, Yuichi Yamazaki, Naoshi Sakuma, Mariko Suzuki
  • Publication number: 20160086890
    Abstract: Wiring comprises a multilayer graphene including graphene sheets, an interlayer substance disposed between layers of the multilayer graphene, and an organic compound layer connected to a side surface of the multilayer graphene. The organic compound layer contains a photoisomerizable organic group connected to the multilayer graphene.
    Type: Application
    Filed: September 1, 2015
    Publication date: March 24, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hisao MIYAZAKI, Tadashi SAKAI
  • Publication number: 20160086891
    Abstract: Graphene wiring of an embodiment has a graphene intercalation compound including a multilayer graphene having graphene sheets stacked therein and an interlayer substance disposed between layers of the multilayer graphene, and an interlayer cross-linked layer connected to a side surface of the multilayer graphene. The interlayer cross-linked layer has a cross-linked molecular structure including multiple bonded molecules cross-linking the graphene sheets included in the multilayer graphene.
    Type: Application
    Filed: September 1, 2015
    Publication date: March 24, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hisao MIYAZAKI, Tadashi SAKAI, Yuichi YAMAZAKI, Masayuki KATAGIRI