Patents by Inventor Hisashi Ohtani

Hisashi Ohtani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8928081
    Abstract: A semiconductor integrated circuit having a high withstand voltage TFT and a TFT which is capable of operating at high speed in a circuit of thin film transistors (TFT) and methods for fabricating such circuit will be provided. A gate insulating film of the TFT required to operate at high speed (e.g., TFT used for a logic circuit) is relatively thinned less than a gate insulating film of the TFT which is required to have high withstand voltage (e.g., TFT used for switching high voltage signals).
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: January 6, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hisashi Ohtani
  • Publication number: 20140327020
    Abstract: It is an object of the invention to provide a light emitting device in which burden on a light emitting element having low luminous efficiency is relieved, and the deterioration of a light emitting element, the reduction in color reproduction due to the deteriorated light emitting element, and increase in electric power consumption can be suppressed. A light emitting device according to the invention has light emitting elements each of which emits one of colors corresponding to three primary colors. Further, one feature of the light emitting device according to the invention has a light emitting element which emits a neutral color. The light emitting device according to the invention has a structure in which a plurality of pixels having light emitting elements each of which emits one of colors corresponding to three primary colors, and a light emitting element which emits a neutral color as one group, are arranged.
    Type: Application
    Filed: July 22, 2014
    Publication date: November 6, 2014
    Inventor: Hisashi Ohtani
  • Patent number: 8872331
    Abstract: A semiconductor device capable of wireless communication, which has high reliability in terms of resistance to external force, in particular, pressing force and can prevent electrostatic discharge in an integrated circuit without preventing reception of an electric wave. The semiconductor device includes an on-chip antenna connected to the integrated circuit and a booster antenna which transmits a signal or power included in a received electric wave to the on-chip antenna without contact. In the semiconductor device, the integrated circuit and the on-chip antenna are interposed between a pair of structure bodies formed by impregnating a fiber body with a resin. One of the structure bodies is provided between the on-chip antenna and the booster antenna. A conductive film having a surface resistance value of approximately 106 to 1014 ?/cm2 is formed on at least one surface of each structure body.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: October 28, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato, Takaaki Koen, Yuto Yakubo, Makoto Yanagisawa, Hisashi Ohtani, Eiji Sugiyama, Nozomi Horikoshi
  • Patent number: 8860899
    Abstract: A metal interconnection is located in the same layer as a source line and connected to the drain of a thin-film transistor. An interlayer insulating film is constituted of at least lower and upper insulating layers and formed between a conductive coating and the source line. According to one aspect of the invention, an auxiliary capacitor is formed by the metal interconnection and the conductive coating serving as both electrodes and at least the lower insulating layer serving as a dielectric. The auxiliary capacitor is formed in a region of the interlayer insulating film in which the upper insulating layer has been removed by etching.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: October 14, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Yasushi Ogata, Yoshiharu Hirakata
  • Publication number: 20140291667
    Abstract: A novel display device capable of excellent reflective display is provided. The display device includes a transistor including a gate electrode layer, a gate insulating layer over the gate electrode layer, a semiconductor layer over the gate insulating layer, and a source electrode layer and a drain electrode layer over the gate insulating layer and the semiconductor layer; a reflective electrode layer on the same plane as the source electrode layer and the drain electrode layer; a coloring layer overlapping with the reflective electrode layer; a pixel electrode layer overlapping with the coloring layer; and an anti-oxidation conductive layer connected to one of the source electrode layer and the drain electrode layer. The pixel electrode layer is connected to the transistor through the anti-oxidation conductive layer.
    Type: Application
    Filed: March 18, 2014
    Publication date: October 2, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masataka Nakada, Hidenori Mori, Hisashi Ohtani
  • Publication number: 20140247412
    Abstract: A semiconductor device includes TFTs designed in accordance with characteristics of circuits. In a first structure of the invention, the TFT is formed by using a crystalline silicon film made of a unique crystal structure body. The crystal structure body has a structure in which rod-like or flattened rod-like crystals grow in a direction parallel to each other. In a second structure of the invention, growth distances of lateral growth regions are made different from each other in accordance with channel lengths, of the TFTs. By this, characteristics of TFTs formed in one lateral growth region can be made as uniform as possible.
    Type: Application
    Filed: May 12, 2014
    Publication date: September 4, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani
  • Patent number: 8809133
    Abstract: There is provided a technique to form a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film. A catalytic element for facilitating crystallization of an amorphous semiconductor thin film is added to the amorphous semiconductor thin film, and a heat treatment is carried out to obtain a crystalline semiconductor thin film. After the crystalline semiconductor thin film is irradiated with ultraviolet light or infrared light, a heat treatment at a temperature of 900 to 1200° C. is carried out in a reducing atmosphere. The surface of the crystalline semiconductor thin film is extremely flattened through this step, defects in crystal grains and crystal grain boundaries disappear, and the single crystal semiconductor thin film or substantially single crystal semiconductor thin film is obtained.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: August 19, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Tamae Takano
  • Patent number: 8791629
    Abstract: It is an object of the invention to provide a light emitting device in which burden on a light emitting element having low luminous efficiency is relieved, and the deterioration of a light emitting element, the reduction in color reproduction due to the deteriorated light emitting element, and increase in electric power consumption can be suppressed. A light emitting device according to the invention has light emitting elements each of which emits one of colors corresponding to three primary colors. Further, one feature of the light emitting device according to the invention has a light emitting element which emits a neutral color. The light emitting device according to the invention has a structure in which a plurality of pixels having light emitting elements each of which emits one of colors corresponding to three primary colors, and a light emitting element which emits a neutral color as one group, are arranged.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: July 29, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hisashi Ohtani
  • Patent number: 8723182
    Abstract: A semiconductor device includes TFTs designed in accordance with characteristics of circuits. In a first structure of the invention, the TFT is formed by using a crystalline silicon film made of a unique crystal structure body. The crystal structure body has a structure in which rod-like or flattened rod-like crystals grow in a direction parallel to each other. In a second structure of the invention, growth distances of lateral growth regions are made different from each other in accordance with channel lengths, of the TFTs. By this, characteristics of TFTs formed in one lateral growth region can be made as uniform as possible.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: May 13, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani
  • Publication number: 20140120996
    Abstract: An object is to provide a card game machine capable of enhancing gameplay. A card game machine has a game board including a plurality of reader/writers configured to communicate with a semiconductor device which is mounted on a card and capable of wireless communication, and a control device connected to the reader/writer and configured to determine the position or orientation of the card or whether the card is put face up or down based on a signal from the reader/writer. By arrangement of a plurality of reader/writers and RF chips in the game board, not only data of the card but also signal strength can be detected, and the detailed position of an RF chip of the card which is placed on the game board can be specified.
    Type: Application
    Filed: January 2, 2014
    Publication date: May 1, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hisashi OHTANI
  • Patent number: 8698160
    Abstract: The object of the present invention is to form a low-concentration impurity region with good accuracy in a top gate type TFT. Phosphorus is added to a semiconductor layer by using a pattern made of a conductive film as a mask to form an N-type impurity region in a self-alignment manner. A positive photoresist is applied to a substrate so as to cover the pattern and then is exposed to light applied to the back of the substrate and then is developed, whereby a photoresist 110 is formed. The pattern is etched by using the photoresist pattern as an etching mask to form a gate electrode. A channel forming region, a source region, a drain region, and low-concentration impurity regions, are formed in the semiconductor layer in a self-alignment manner by using the gate electrode as a doping mask.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: April 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hisashi Ohtani
  • Patent number: 8696808
    Abstract: Each region, which should be left on a substrate after patterning, of a semiconductor film is grasped in accordance with a mask. Then, each region to be scanned with laser light is determined so that at least the region to be obtained through the patterning is crystallized, and a beam spot is made to hit the region to be scanned, thereby partially crystallizing the semiconductor film. Each portion with low output energy of the beam spot is shielded by a slit. In the present invention, the laser light is not scanned and irradiated onto the entire surface of the semiconductor film but is scanned such that at least each indispensable portion is crystallized to a minimum. With the construction described above, it becomes possible to save time taken to irradiate the laser light onto each portion to be removed through the patterning after the crystallization of the semiconductor film.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: April 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Masaaki Hiroki, Koichiro Tanaka, Aiko Shiga, Satoshi Murakami, Mai Akiba
  • Patent number: 8632391
    Abstract: An object is to provide a card game machine capable of enhancing gameplay. A card game machine has a game board including a plurality of reader/writers configured to communicate with a semiconductor device which is mounted on a card and capable of wireless communication, and a control device connected to the reader/writer and configured to determine the position or orientation of the card or whether the card is put face up or down based on a signal from the reader/writer. By arrangement of a plurality of reader/writers and RF chips in the game board, not only data of the card but also signal strength can be detected, and the detailed position of an RF chip of the card which is placed on the game board can be specified.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: January 21, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hisashi Ohtani
  • Patent number: 8603870
    Abstract: A semiconductor device having a CMOS structure, wherein, in manufacturing a CMOS circuit, an impurity element which imparts p-type conductivity to the active layer of the p-channel type semiconductor device is added before forming the gate insulating film. Then, by applying thermal oxidation treatment to the active layer, the impurity element is subjected to redistribution, and the concentration of the impurity element in the principal surface of the active layer is minimized. The precise control of threshold voltage is enabled by the impurity element that is present in a trace quantity.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: December 10, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Takeshi Fukunaga
  • Patent number: 8592861
    Abstract: It is an object of the present invention to provide a technique to manufacture a highly reliable display device at a low cost with high yield. A display device according to the present invention includes a semiconductor layer including an impurity region of one conductivity type; a gate insulating layer, a gate electrode layer, and a wiring layer in contact with the impurity region of one conductivity type, which are provided over the semiconductor layer; a conductive layer which is formed over the gate insulating layer and in contact with the wiring layer; a first electrode layer in contact with the conductive layer; an electroluminescent layer provided over the first electrode layer; and a second electrode layer, where the wiring layer is electrically connected to the first electrode layer with the conductive layer interposed therebetween.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: November 26, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Hisashi Ohtani, Misako Hirosue
  • Patent number: 8576348
    Abstract: There is disclosed an active matrix reflective liquid crystal display panel on which an active matrix circuit is integrated with peripheral driver circuits. Metal lines in the peripheral driver circuits are formed simultaneously with pixel electrodes. Thus, neither the process sequence nor the structure is complicated.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: November 5, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Jun Koyama, Satoshi Teramoto
  • Publication number: 20130285078
    Abstract: A semiconductor integrated circuit having a high withstand voltage TFT and a TFT which is capable of operating at high speed in a circuit of thin film transistors (TFT) and methods for fabricating such circuit will be provided. A gate insulating film of the TFT required to operate at high speed (e.g., TFT used for a logic circuit) is relatively thinned less than a gate insulating film of the TFT which is required to have high withstand voltage (e.g., TFT used for switching high voltage signals).
    Type: Application
    Filed: March 21, 2013
    Publication date: October 31, 2013
    Inventor: Hisashi Ohtani
  • Publication number: 20130270720
    Abstract: A separation layer and a semiconductor element layer including a thin film transistor are formed. A conductive resin electrically connected to the semiconductor element layer is formed. A first sealing layer including a fiber and an organic resin layer is formed over the semiconductor element layer and the conductive resin. A groove is formed in the first sealing layer, the semiconductor element layer, and the separation layer. A liquid is dropped into the groove to separate the separation layer and the semiconductor element layer. The first sealing layer over the conductive resin is removed to form an opening. A set of the first sealing layer and the semiconductor element layer is divided into a chip. The chip is bonded to an antenna formed over a base material. A second sealing layer including a fiber and an organic resin layer is formed so as to cover the antenna and the chip.
    Type: Application
    Filed: June 7, 2013
    Publication date: October 17, 2013
    Inventors: Tomoyuki AOKI, Takuya TSURUME, Hiroki ADACHI, Nozomi HORIKOSHI, Hisashi OHTANI
  • Publication number: 20130270570
    Abstract: The object of the present invention is to form a low-concentration impurity region with good accuracy in a top gate type TFT. Phosphorus is added to a semiconductor layer by using a pattern made of a conductive film as a mask to form an N-type impurity region in a self-alignment manner. A positive photoresist is applied to a substrate so as to cover the pattern and then is exposed to light applied to the back of the substrate and then is developed, whereby a photoresist 110 is formed. The pattern is etched by using the photoresist pattern as an etching mask to forma gate electrode. A channel forming region, a source region, a drain region, and low-concentration impurity regions, are formed in the semiconductor layer in a self-alignment manner by using the gate electrode as a doping mask.
    Type: Application
    Filed: February 11, 2013
    Publication date: October 17, 2013
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hisashi Ohtani
  • Patent number: 8558370
    Abstract: The present invention provides a semiconductor device which is not easily damaged by external local pressure. The present invention further provides a manufacturing method of a highly-reliable semiconductor device, which is not destroyed by external local pressure, with a high yield. A structure body, in which high-strength fiber of an organic compound or an inorganic compound is impregnated with an organic resin, is provided over an element substrate having a semiconductor element formed using a single crystal semiconductor region, and heating and pressure bonding are performed, whereby a semiconductor device is manufactured, to which the element substrate and the structure body in which the high-strength fiber of an organic compound or an inorganic compound is impregnated with the organic resin are fixed together.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: October 15, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Eiji Sugiyama, Yoshitaka Dozen, Hisashi Ohtani, Takuya Tsurume