Patents by Inventor Hisashi Ohtani

Hisashi Ohtani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8552418
    Abstract: The present invention provides a semiconductor device which is not easily damaged by external local pressure. The present invention further provides a method for manufacturing a highly-reliable semiconductor device, which is not destructed by external local pressure, with a high yield. A structure body, in which high-strength fiber of an organic compound or an inorganic compound is impregnated with an organic resin, is provided over an element layer having a semiconductor element formed using a non-single crystal semiconductor layer, and heating and pressure bonding are performed, whereby a semiconductor device is manufactured, to which the element layer and the structure body in which the high-strength fiber of an organic compound or an inorganic compound is impregnated with the organic resin are firmly fixed together.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: October 8, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Eiji Sugiyama, Yoshitaka Dozen, Hisashi Ohtani, Takuya Tsurume
  • Patent number: 8536784
    Abstract: The inventors have anticipated that there is no problem in employing electron gun deposition as a method of forming a metallic layer on an EL layer of an active matrix light-emitting device because the TFT of the active matrix light-emitting device is disposed below the EL layer. However, since the TFT is extremely sensitive to ionized evaporated particles, the secondary electron, the reflecting electron, and so on generated by the electron gun, while little damage is observed on the EL layer, significant damage is found on the TFT when electron gun deposition is employed. The invention provides an active matrix light-emitting device having superior TFT characteristics (ON current, OFF to current, Vth, S-value, and so on), in which an organic compound layer and a metallic layer (cathode or anode) are formed by means of resistive heating having least influence to the TFT.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: September 17, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masakazu Murakami, Naomi Kawakami, Hisashi Ohtani
  • Patent number: 8531619
    Abstract: A first insulating thin film having a large dielectric constant such as a silicon nitride film is formed so as to cover a source line and a metal wiring that is in the same layer as the source line. A second insulating film that is high in flatness is formed on the first insulating film. An opening is formed in the second insulating film by etching the second insulating film, to selectively expose the first insulating film. A conductive film to serve as a light-interruptive film is formed on the second insulating film and in the opening, whereby an auxiliary capacitor of the pixel is formed between the conductive film and the metal wiring with the first insulating film serving as a dielectric.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: September 10, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Yasushi Ogata
  • Patent number: 8497822
    Abstract: The invention provides a light emitting device which can suppress the reduction of luminance in accordance with the light emission time and light emission at a high luminance. Moreover, the invention relates to a driving method which can suppress the reduction of luminance in accordance with the light emission time and light emission at a high luminance. The light emitting device of the invention can display a plurality of colors of which brightness and chromaticity are different by visually mixing light emission of a plurality of light emitting elements of which light emission colors are different. When a visually mixed display color is formed, a white light emission is exhibited.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: July 30, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Yoshifumi Tanada, Aya Anzai
  • Patent number: 8497508
    Abstract: A wiring line is electrically connected in parallel to an auxiliary wiring line via a plurality of contact holes. The contact holes are formed through an insulating film and arranged in vertical direction to the wiring line. Since the auxiliary wiring line is formed in the same layer as an electrode that constitutes a TFT, the electric resistance of the wiring line can be reduced effectively without increasing the number of manufacturing steps.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: July 30, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Hisashi Ohtani, Yasushi Ogata, Shunpei Yamazaki
  • Patent number: 8482069
    Abstract: An active region, a source region, and a drain region are formed on a single crystal semiconductor substrate or a single crystal semiconductor thin film. Impurity regions called pinning regions are formed in striped form in the active region so as to reach both of the source region and the drain region. Regions interposed between the pinning regions serve as channel forming regions. A tunnel oxide film, a floating gate, a control gate, etc. are formed on the above structure. The impurity regions prevent a depletion layer from expanding from the source region toward the drain region.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: July 9, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Jun Koyama, Takeshi Fukunaga
  • Patent number: 8459561
    Abstract: A separation layer and a semiconductor element layer including a thin film transistor are formed. A conductive resin electrically connected to the semiconductor element layer is formed. A first sealing layer including a fiber and an organic resin layer is formed over the semiconductor element layer and the conductive resin. A groove is formed in the first sealing layer, the semiconductor element layer, and the separation layer. A liquid is dropped into the groove to separate the separation layer and the semiconductor element layer. The first sealing layer over the conductive resin is removed to form an opening. A set of the first sealing layer and the semiconductor element layer is divided into a chip. The chip is bonded to an antenna formed over a base material. A second sealing layer including a fiber and an organic resin layer is formed so as to cover the antenna and the chip.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: June 11, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoyuki Aoki, Takuya Tsurume, Hiroki Adachi, Nozomi Horikoshi, Hisashi Ohtani
  • Patent number: 8440509
    Abstract: A semiconductor device and a process for producing the same, the semiconductor device comprising two conductive layers provided as separate layers, and an insulating layer sandwiched by the two conductive layers, in which the two conductive layers are electrically connected to each other with an embedded conductive layer or an oxide conductive layer provided as filling an opening formed in the insulating layer, and the embedded conductive layer comprises an organic resin film containing a conductive material dispersed therein or an inorganic film containing a conductive material dispersed therein.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: May 14, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Misako Nakazawa, Satoshi Murakami
  • Patent number: 8405149
    Abstract: A semiconductor integrated circuit having a high withstand voltage TFT and a TFT which is capable of operating at high speed in a circuit of thin film transistors (TFT) and methods for fabricating such circuit will be provided. A gate insulating film of the TFT required to operate at high speed (e.g., TFT used for a logic circuit) is relatively thinned less than a gate insulating film of the TFT which is required to have high withstand voltage (e.g., TFT used for switching high voltage signals).
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: March 26, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hisashi Ohtani
  • Patent number: 8405789
    Abstract: There is disclosed an active matrix reflective liquid crystal display panel on which an active matrix circuit is integrated with peripheral driver circuits. Metal lines in the peripheral driver circuits are formed simultaneously with pixel electrodes. Thus, neither the process sequence nor the structure is complicated.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: March 26, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Jun Koyama, Satoshi Teramoto
  • Patent number: 8405090
    Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: March 26, 2013
    Assignee: Semiconductor Energy Labortory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani
  • Patent number: 8384084
    Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: February 26, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toru Mitsuki, Akiharu Miyanaga, Yasushi Ogata
  • Publication number: 20130037884
    Abstract: An active region, a source region, and a drain region are formed on a single crystal semiconductor substrate or a single crystal semiconductor thin film. Impurity regions called pinning regions are formed in striped form in the active region so as to reach both of the source region and the drain region. Regions interposed between the pinning regions serve as channel forming regions. A tunnel oxide film, a floating gate, a control gate, etc. are formed on the above structure. The impurity regions prevent a depletion layer from expanding from the source region toward the drain region.
    Type: Application
    Filed: July 16, 2012
    Publication date: February 14, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Hisashi OHTANI, Jun KOYAMA, Takeshi FUKUNAGA
  • Patent number: 8373173
    Abstract: The object of the present invention is to form a low-concentration impurity region with good accuracy in a top gate type TFT. Phosphorus is added to a semiconductor layer by using a pattern made of a conductive film as a mask to form an N-type impurity region in a self-alignment manner. A positive photoresist is applied to a substrate so as to cover the pattern and then is exposed to light applied to the back of the substrate and then is developed, whereby a photoresist 110 is formed. The pattern is etched by using the photoresist pattern as an etching mask to form a gate electrode. A channel forming region, a source region, a drain region, and low-concentration impurity regions, are formed in the semiconductor layer in a self-alignment manner by using the gate electrode as a doping mask.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: February 12, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hisashi Ohtani
  • Patent number: 8368142
    Abstract: A semiconductor device having performance comparable with a MOSFET is provided. An active layer of the semiconductor device is formed by a crystalline silicon film crystallized by using a metal element for promoting crystallization, and further by carrying out a heat treatment in an atmosphere containing a halogen element to carry out gettering of the metal element. The active layer after this process is constituted by an aggregation of a plurality of needle-shaped or column-shaped crystals. A semiconductor device manufactured by using this crystalline structure has extremely high performance.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: February 5, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Jun Koyama, Takeshi Fukunaga
  • Patent number: 8350466
    Abstract: It is an object of the present invention to provide a technology for manufacturing a highly reliable display device at a low cost with high yield. In the present invention, a spacer is formed over a pixel electrode, thereby protecting the pixel electrode layer from a mask in formation of an electroluminescent layer. In addition, since a layer that includes an organic material that has water permeability is sealed in a display device with a sealing material and the sealing material and the layer that includes the organic material are not in contact, deterioration of a light-emitting element due to a contaminant such as water can be prevented. The sealing material is formed in a portion of a driver circuit region in the display device, and thus, the narrower frame margin of the display device can also be accomplished.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: January 8, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Murakami, Hisashi Ohtani, Shunpei Yamazaki
  • Publication number: 20130001581
    Abstract: A first insulating thin film having a large dielectric constant such as a silicon nitride film is formed so as to cover a source line and a metal wiring that is in the same layer as the source line. A second insulating film that is high in flatness is formed on the first insulating film. An opening is formed in the second insulating film by etching the second insulating film, to selectively expose the first insulating film. A conductive film to serve as a light-interruptive film is formed on the second insulating film and in the opening, whereby an auxiliary capacitor of the pixel is formed between the conductive film and the metal wiring with the first insulating film serving as a dielectric.
    Type: Application
    Filed: August 16, 2012
    Publication date: January 3, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hisashi OHTANI, Yasushi OGATA
  • Patent number: 8338931
    Abstract: In the present application, is disclosed a method of manufacturing a flexible semiconductor device having an excellent reliability and tolerance to the loading of external pressure. The method includes the steps of: forming a separation layer over a substrate having an insulating surface; forming an element layer including a semiconductor element comprising a non-single crystal semiconductor layer, over the separation layer; forming an organic resin layer over the element layer; providing a fibrous body formed of an organic compound or an inorganic compound on the organic resin layer; heating the organic resin layer; and separating the element layer from the separation layer. This method allows the formation of a flexible semiconductor device having a sealing layer in which the fibrous body is impregnated with the organic resin.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: December 25, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshitaka Dozen, Eiji Sugiyama, Hisashi Ohtani, Takuya Tsurume
  • Patent number: 8334645
    Abstract: It is an object of the invention to provide a light emitting device in which burden on a light emitting element having low luminous efficiency is relieved, and the deterioration of a light emitting element, the reduction in color reproduction due to the deteriorated light emitting element, and increase in electric power consumption can be suppressed. A light emitting device according to the invention has light emitting elements each of which emits one of colors corresponding to three primary colors. Further, one feature of the light emitting device according to the invention has a light emitting element which emits a neutral color. The light emitting device according to the invention has a structure in which a plurality of pixels having light emitting elements each of which emits one of colors corresponding to three primary colors, and a light emitting element which emits a neutral color as one group, are arranged.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: December 18, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hisashi Ohtani
  • Publication number: 20120299009
    Abstract: The object of the present invention is to form a low-concentration impurity region with good accuracy in a top gate type TFT. Phosphorus is added to a semiconductor layer by using a pattern made of a conductive film as a mask to form an N-type impurity region in a self-alignment manner. A positive photoresist is applied to a substrate so as to cover the pattern and then is exposed to light applied to the back of the substrate and then is developed, whereby a photoresist 110 is formed. The pattern is etched by using the photoresist pattern as an etching mask to form a gate electrode. A channel forming region, a source region, a drain region, and low-concentration impurity regions, are formed in the semiconductor layer in a self-alignment manner by using the gate electrode as a doping mask.
    Type: Application
    Filed: August 6, 2012
    Publication date: November 29, 2012
    Inventor: Hisashi Ohtani