Patents by Inventor HO-FAN KANG
HO-FAN KANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9875025Abstract: Systems and methods for retaining data are disclosed in which refresh copy operations are performed on data stored in non-volatile solid-state memory. A controller may be configured to maintain a list of physical memory locations, the list sorted by a least recently used criterion. The controller may select a first entry from a top of the list and perform a refresh operation to copy data stored in a current physical memory location associated with the first entry to a new physical memory location, and may remove the first entry from the top of the list and add a new entry associated with the new physical memory location to a bottom of the list. The controller may repeat the select, perform, remove and add steps for a plurality of entries in the list, and the steps may be timed such that all refresh operations are performed for all of the plurality of entries within a set period of time.Type: GrantFiled: September 14, 2015Date of Patent: January 23, 2018Assignee: Western Digital Technologies, IncInventors: Mei-Man L. Syu, Matthew Call, Ho-Fan Kang, Lan D. Phan
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Patent number: 9678671Abstract: Embodiments of the invention are directed to optimizing the selection of memory blocks for garbage collection in solid state devices to efficiently maximize the amount of memory freed by garbage collection operations. The systems and methods disclosed herein provide for the efficient selection of optimal or near-optimal garbage collection candidate blocks, with the most optimal selection defined as block(s) with the most invalid pages. In one embodiment, a controller classifies memory blocks into various invalid block pools by the amount of invalid pages each block contains. In one embodiment, the controller selects for garbage collection a block from a non-empty pool of blocks with the highest minimum amount of invalid pages. One or more of the pools have minimum thresholds that can be dynamically adjusted according to an observed usage condition, such as a change of an over-provisioning amount in the storage state device.Type: GrantFiled: October 12, 2015Date of Patent: June 13, 2017Assignee: Western Digital Technologies, Inc.Inventors: Ho-Fan Kang, Jerry Lo, Johnny Lam
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Patent number: 9652379Abstract: Embodiments of the invention are directed to enabling concurrent commands from command requesters in a non-volatile solid-state storage subsystem in a manner that reduces contentions among the commands. Embodiments group blocks of memory into multiple sets of superblocks and associate a command requester to each superblock set. In one embodiment, the superblock sets are dynamically associated with a requester. In one embodiment, the superblock sets are dynamically associated with requesters based in part on at least one of internal memory management needs and host command throughput. In one embodiment, an erase command is executed on a superblock within a set and a simultaneous write command is executed on a superblock within another set.Type: GrantFiled: April 30, 2014Date of Patent: May 16, 2017Assignee: Western Digital Technologies, Inc.Inventors: Mei-Man L. Syu, Matthew Call, Ho-Fan Kang, Lan D. Phan
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Patent number: 9405675Abstract: Embodiments of the invention are directed to enable simultaneous or nearly simultaneous execution of internal and host-issued commands in a non-volatile storage subsystem while maintaining data consistency. Embodiments maintain validity information on data residing at physical addresses as well as logical to physical address mappings in the solid-state storage subsystem. In one embodiment, a controller within the storage subsystem selectively cancels internal commands that it determines to be writing data that has been rendered invalid by another command. In one embodiment, the determination is made by consulting the validity information kept by the controller in an invalid page table.Type: GrantFiled: June 12, 2014Date of Patent: August 2, 2016Assignee: Western Digital Technologies, Inc.Inventors: Ho-Fan Kang, Lan D. Phan
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Publication number: 20160103617Abstract: Embodiments of the invention are directed to optimizing the selection of memory blocks for garbage collection in solid state devices to efficiently maximize the amount of memory freed by garbage collection operations. The systems and methods disclosed herein provide for the efficient selection of optimal or near-optimal garbage collection candidate blocks, with the most optimal selection defined as block(s) with the most invalid pages. In one embodiment, a controller classifies memory blocks into various invalid block pools by the amount of invalid pages each block contains. In one embodiment, the controller selects for garbage collection a block from a non-empty pool of blocks with the highest minimum amount of invalid pages. One or more of the pools have minimum thresholds that can be dynamically adjusted according to an observed usage condition, such as a change of an over-provisioning amount in the storage state device.Type: ApplicationFiled: October 12, 2015Publication date: April 14, 2016Inventors: Ho-Fan KANG, Jerry LO, Johnny LAM
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Publication number: 20160004446Abstract: Systems and methods for retaining data in non-volatile solid-state memory are disclosed in which refresh copy operations are performed on data stored in non-volatile solid-state memory. A controller may be configured to issue copy commands and to maintain usage data on a storage subsystem. A refresh copy operation helps ensure that data written to memory retain integrity by causing data to be programmed again onto the memory, which minimizes the risk of data error caused by electron leak in the non-volatile solid-state memory. The controller may be configured to maintain a list of physical memory locations storing data in non-volatile solid-state memory array, where the list is sorted by a least recently used criterion. In one embodiment, the controller may select a first entry from a top of the list for processing and issue a copy command stored in a current physical memory location associated with the first entry to a new physical memory location.Type: ApplicationFiled: September 14, 2015Publication date: January 7, 2016Inventors: Mei-Man L. SYU, Matthew CALL, Ho-Fan KANG, Lan D. PHAN
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Patent number: 9158670Abstract: Embodiments of the invention are directed to optimizing the selection of memory blocks for garbage collection in solid state devices to efficiently maximize the amount of memory freed by garbage collection operations. The systems and methods disclosed herein provide for the efficient selection of optimal or near-optimal garbage collection candidate blocks, with the most optimal selection defined as block(s) with the most invalid pages. In one embodiment, a controller classifies memory blocks into various invalid block pools by the amount of invalid pages each block contains. In one embodiment, the controller selects for garbage collection a block from a non-empty pool of blocks with the highest minimum amount of invalid pages. One or more of the pools have minimum thresholds that can be dynamically adjusted according to an observed usage condition, such as a change of an over-provisioning amount in the storage state device.Type: GrantFiled: June 30, 2011Date of Patent: October 13, 2015Assignee: Western Digital Technologies, Inc.Inventors: Ho-Fan Kang, Jerry Lo, Johnny Lam
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Patent number: 9135166Abstract: Systems and methods for retaining data in non-volatile solid-state memory are disclosed in which refresh copy operations are performed on data stored in non-volatile solid-state memory. A controller can comprise a data retention module configured to issue copy commands within different periods of time and to maintain usage data on a storage subsystem. A refresh copy operation helps ensure that data written to memory retain integrity by causing data to be programmed again onto the memory. Execution of refresh copy commands may be prioritized over other commands based on a remaining length of time. One or more data structures may be used to determine memory blocks that require refresh copy operations. In one embodiment, a validity bit array is used to track blocks that contain valid data. In another embodiment, a least recently used list is used to track blocks that have been least recently written.Type: GrantFiled: November 22, 2013Date of Patent: September 15, 2015Assignee: Western Digital Technologies, Inc.Inventors: Mei-Man L. Syu, Matthew Call, Ho-Fan Kang, Lan D. Phan
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Patent number: 9075708Abstract: The present disclosure is directed to managing write commands for a storage system implementing address indirection. In some storage systems, a mapping table that provides logical-to-physical mapping may have individual entries that each references a logical address size that exceeds the size of an atomic write to the storage media. In such systems, a write to a logical address is not atomic as it may require several discrete physical writes that may individually fail. The techniques presented employ several pre-commit and post-commit actions to save data that enables the storage system to make writes to these logical addresses atomic and prevent undue delay on powerup.Type: GrantFiled: June 30, 2011Date of Patent: July 7, 2015Assignee: Western Digital Technologies, Inc.Inventors: Ho-Fan Kang, Stephen P. Hack, Jerry Lo, Frederick H. Adi, Lan D. Phan
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Patent number: 9026716Abstract: Methods and systems for optimizing the selection of memory blocks for garbage collection to maximize the amount of memory freed by garbage collection operations are disclosed. Some of these systems and methods provide for the efficient selection of optimal or near-optimal garbage collection candidate blocks, with the most optimal selection defined as block(s) with the most invalid pages. In some cases, a controller classifies memory blocks into various invalid block pools by the amount of invalid pages each block contains. When garbage collection is performed, the controller selects a block from a non-empty pool of blocks with the highest minimum amount of invalid pages. The pools facilitate the optimal or near-optimal selection of garbage collection candidate blocks in an efficient manner and the data structure of the pools can be implemented with bitmasks, which take minimal space in memory.Type: GrantFiled: May 12, 2010Date of Patent: May 5, 2015Assignee: Western Digital Technologies, Inc.Inventors: Ho-Fan Kang, Alan Chingtao Kan
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Patent number: 9021192Abstract: Embodiments of this disclosure relate to improving solid-state non-volatile memory management. Embodiments improve the management of solid-state non-volatile memory by providing a central manager responsible for receiving requests from media access requesters. In embodiments, the central manager updates requests with a physical address corresponding to a logical address for a request. In embodiments, the central manager is the only entity updating a mapping table and invalid page table for the system. In embodiments, the central manager may also throttle or prioritize requests originating from two or more requesters to change the ratio of requests executed from each requester.Type: GrantFiled: June 17, 2011Date of Patent: April 28, 2015Assignee: Western Digital Technologies, Inc.Inventors: Ho-Fan Kang, Lan D. Phan
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Patent number: 8990484Abstract: N page counters are associated with N blocks in the flash subsystem. Each of the N page counters indicates a count of invalid pages in each corresponding block in the N blocks. A max heap structure is formed over the N page counters. At least one of the N page counters is updated each time the count changes. The max heap structure is updated each time the at least one of the N page counters is updated. A maximum value is retrieved from a highest level of the max heap structure. The max heap structure is traversed down to lowest level using the maximum value at each level until reaching the lowest level. The lowest level corresponds to N page counters. One of the N blocks having associated page counter corresponds to the maximum value is identified as a candidate for block erasure.Type: GrantFiled: December 14, 2012Date of Patent: March 24, 2015Assignee: Virtium Technology, IncInventor: Ho-Fan Kang
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Patent number: 8924629Abstract: A non-volatile storage system is disclosed which provides a mapping table which includes a granularity which does not correspond to the page size of a non-volatile storage array. A reduced mapping table granularity enables more than one mapping entry to exist in a single page on the solid-state array. A write command which does not exceed a mapping table entry can invalidate only a portion of the written page, and can be combined with a second write command to write a new page of the solid-state array.Type: GrantFiled: June 7, 2011Date of Patent: December 30, 2014Assignee: Western Digital Technologies, Inc.Inventors: Matthew Call, Robert L. Horn, Mei-Man L. Syu, Lan D. Phan, John A. Morrison, Ho-Fan Kang
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Patent number: 8898373Abstract: Embodiments of the invention are directed to systems and methods for improving wear leveling performance in solid-state memory. The embodiments described herein make more consistent the number of wear leveling operations that needs to be performed, so that sudden spikes in the number wear leveling operations may be reduced in solid-state memory. In one embodiment, a staggered threshold-based wear leveling approach is used to spread out the execution of wear leveling operations that otherwise would have been triggered in clusters. Under the staggered threshold-based approach, wear leveling is periodically triggered by different wear leveling thresholds that are associated with various units of solid-state memory such as a group of blocks, so that only a certain amount of units are wear leveled at any given time.Type: GrantFiled: June 29, 2011Date of Patent: November 25, 2014Assignee: Western Digital Technologies, Inc.Inventors: Ho-Fan Kang, Cliff Pajaro
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Patent number: 8782327Abstract: Embodiments of the invention are directed to enable simultaneous or nearly simultaneous execution of internal and host-issued commands in a non-volatile storage subsystem while maintaining data consistency. Embodiments maintain validity information on data residing at physical addresses as well as logical to physical address mappings in the solid-state storage subsystem. In one embodiment, a controller within the storage subsystem selectively cancels internal commands that it determines to be writing data that has been rendered invalid by another command. In one embodiment, the determination is made by consulting the validity information kept by the controller in an invalid page table.Type: GrantFiled: May 11, 2010Date of Patent: July 15, 2014Assignee: Western Digital Technologies, Inc.Inventors: Ho-Fan Kang, Lan D. Phan
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Patent number: 8769190Abstract: Embodiments of the invention are directed to enabling concurrent commands from command requesters in a non-volatile solid-state storage subsystem in a manner that reduces contentions among the commands. Embodiments group blocks of memory into multiple sets of superblocks and associate a command requester to each superblock set. In one embodiment, the superblock sets are dynamically associated with a requester. In one embodiment, the superblock sets are dynamically associated with requesters based in part on at least one of internal memory management needs and host command throughput. In one embodiment, an erase command is executed on a superblock within a set and a simultaneous write command is executed on a superblock within another set.Type: GrantFiled: August 19, 2011Date of Patent: July 1, 2014Assignee: Western Digital Technologies, Inc.Inventors: Mei-Man L. Syu, Matthew Call, Ho-Fan Kang, Lan D. Phan
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Publication number: 20140173176Abstract: N page counters are associated with N blocks in the flash subsystem. Each of the N page counters indicates a count of invalid pages in each corresponding block in the N blocks. A max heap structure is formed over the N page counters. At least one of the N page counters is updated each time the count changes. The max heap structure is updated each time the at least one of the N page counters is updated. A maximum value is retrieved from a highest level of the max heap structure. The max heap structure is traversed down to lowest level using the maximum value at each level until reaching the lowest level. The lowest level corresponds to N page counters. One of the N blocks having associated page counter corresponds to the maximum value is identified as a candidate for block erasure.Type: ApplicationFiled: December 14, 2012Publication date: June 19, 2014Applicant: Virtium Technology, Inc.Inventor: Ho-Fan Kang
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Publication number: 20140173175Abstract: An embodiment is a method and apparatus to provide an optimization of commands in a flash device. Commands sent by at least a top-level processor to a flash device are buffered in a buffer. The buffered commands are analyzed for an optimizing condition. The commands are aggregated if the optimizing condition is met. The aggregated commands are sent to the flash device.Type: ApplicationFiled: December 14, 2012Publication date: June 19, 2014Applicant: Virtium Technology, Inc.Inventors: Ho-Fan Kang, Lan Dinh Phan
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Patent number: 8725931Abstract: Embodiments of the invention are directed to a storage subsystem comprising a non-volatile solid-state memory array and a controller. In one embodiment, the controller includes a system operation module configured to manage system memory operations and a queue configured to receive memory commands from a host system and the system operation module. The controller is configured to execute, in the memory array, memory commands from the queue in a sequence that is based at least in part on a throttling ratio provided by the system operation module.Type: GrantFiled: March 26, 2010Date of Patent: May 13, 2014Assignee: Western Digital Technologies, Inc.Inventor: Ho-Fan Kang
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Patent number: 8612669Abstract: Systems and methods for retaining data in non-volatile solid-state are disclosed in which refresh copy operations are performed on data stored in non-volatile solid-state memory. A controller can comprise a data retention module configured to issue copy commands within different periods of time, and to maintain usage data on a storage subsystem. A refresh copy operation helps ensure that data written to memory retain integrity by causing data to be programmed again onto the memory, which minimizes the risk of data error caused by electron leak in the non-volatile solid-state memory. One or more data structures may be used to determine memory blocks that require refresh copy operations. In one embodiment, a validity bit array is used to track blocks that contain valid data. In another embodiment, a least recently used list is used to track blocks that have been least recently written.Type: GrantFiled: June 28, 2010Date of Patent: December 17, 2013Assignee: Western Digital Technologies, Inc.Inventors: Mei-Man L. Syu, Matthew Call, Ho-Fan Kang, Lan D. Phan