Patents by Inventor HO-FAN KANG

HO-FAN KANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8612804
    Abstract: Embodiments of the invention are directed to systems and methods for improving wear leveling performance in solid-state memory. The embodiments described herein make more consistent the number of wear leveling operations that need to be performed, so that sudden spikes in the number wear leveling operations may be reduced in solid-state memory. In one embodiment, a rule-based wear leveling approach is used to spread out the execution of wear leveling operations that otherwise would have been triggered in clusters. Under the rule-based approach, wear leveling is periodically triggered by a specified interval of erase counts associated with a unit of solid-state memory such as a group of blocks, rather than by a threshold based on erase counts.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: December 17, 2013
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ho-Fan Kang, Cliff Pajaro
  • Patent number: 8458435
    Abstract: Embodiments of the invention are directed to systems and methods for detecting sequential write threads in non-volatile storage media. The embodiments described herein detect write commands directed to a range of logical addresses corresponding to a write thread. Upon detection of a write command directed to a write thread, the write command is assigned a physical write address associated with the write thread. Identification of write threads can be implemented with a hardware component which performs comparison operations between the write command address range and the write thread address range.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: June 4, 2013
    Assignee: Western Digital Technologies, Inc.
    Inventors: Charles P. Rainey, III, Dominic S. Suryabudi, Ho-Fan Kang
  • Publication number: 20110283049
    Abstract: Embodiments of the invention are directed to optimizing the selection of memory blocks for garbage collection to maximize the amount of memory freed by garbage collection operations. The systems and methods disclosed herein provide for the efficient selection of optimal or near-optimal garbage collection candidate blocks, with the most optimal selection defined as block(s) with the most invalid pages. In one embodiment, a controller classifies memory blocks into various invalid block pools by the amount of invalid pages each block contains. When garbage collection is performed, the controller selects a block from a non-empty pool of blocks with the highest minimum amount of invalid pages. The pools facilitate the optimal or near-optimal selection of garbage collection candidate blocks in an efficient manner and the data structure of the pools can be implemented with bitmasks, which take minimal space in memory.
    Type: Application
    Filed: May 12, 2010
    Publication date: November 17, 2011
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: HO-FAN KANG, ALAN CHINGTAO KAN