Abstract: An internal voltage generation circuit includes an initial driver configured to sense an internal voltage for a predetermined period of time from the beginning of an active mode and to drive a driving signal, which is used for driving the internal voltage to a level of an external voltage, to a first level, an initial driving terminator configured to drive the driving signal to a second level if the internal voltage is higher than a target level, and a comparison driver configured to drive the driving signal so as to maintain the internal voltage at a target level.

Abstract: An apparatus for controlling an activation of semiconductor integrated circuit includes: an active control unit configured to generate active control signal for determining activation of banks; and a plurality of active signal generating units configured to input the active control signal commonly, and generate active signals for activating the banks to according to the active control signal. According to this structure, it is possible to reduce current consumption to a minimum in a refresh mode, to easily arrange signal lines, and thus to effectively use extra space.

Abstract: A bulk bias voltage generating device is configured to generate a first bulk bias voltage in a deep power down mode and a second bulk bias voltage in a normal mode. The first bulk bias voltage comprises an internal voltage level, and the second bulk bias voltage comprises an external voltage level.

Abstract: A semiconductor memory apparatus includes a first bank block including a first bank group, a second bank block including a second bank group, and an address control unit that receives an address signal to selectively provide a decoded row address signal to the first bank block or the second bank block in response to a bank address signal.

Abstract: A refresh period signal generator with a digital temperature information generation function includes a temperature information generating part configured to generate temperature information by using a first period signal and a second period signal, a refresh period signal generating part configured to output a refresh period signal by selecting one signal having a shorter period between the first period signal and the second period signal, and an operation timing control part operating the temperature information generating part and the refresh period signal generating part at a predetermined timing.

Abstract: An internal voltage generation circuit includes an initial driver configured to sense an internal voltage for a predetermined period of time from the beginning of an active mode and to drive a driving signal, which is used for driving the internal voltage to a level of an external voltage, to a first level, an initial driving terminator configured to drive the driving signal to a second level if the internal voltage is higher than a target level, and a comparison driver configured to drive the driving signal so as to maintain the internal voltage at a target level.

Abstract: In a skew signal generation circuit, a pad is connected to an external resistor and a code generator compares a voltage of the pad with a reference voltage to generate a plurality of codes. A skew signal extractor extracts a skew signal from the codes, the skew signal containing information about a current characteristic of a MOS transistor. A driver calibrates a drivability in response to the skew signal.

Abstract: A periodic signal generating circuit which is dependent upon temperature for establishing a temperature independent refresh frequency is presented The periodic signal generating circuit includes a reference voltage generating unit and a periodic signal generating unit. The reference voltage generating unit produces a reference voltage which exhibits a variable voltage level in response to temperature. The periodic signal generating unit produces a periodic signal in response to a set voltage to determine the reference voltage and an oscillation period, wherein a transition timing of the set voltage is controlled by the reference voltage. As a result the periodic signal has a relatively constant period which can be produced regardless of the temperature variation.

Abstract: Disclosed is a circuit for generating pulses for a semiconductor apparatus. The circuit for generating pulses for a semiconductor apparatus includes a temperature sensor, a temperature signal decoder, and a pulse generator. The temperature sensor senses the temperature of a memory chip and converts the temperature into a digital code combination so as to output a plurality of temperature information signals. The temperature signal decoder decodes the plurality of temperature information signals so as to output a delay control signal. The pulse generator outputs an overdriving pulse signal in response to a sense amplifier driving signal and the delay control signal.

Abstract: A data output apparatus includes a driver driving unit configured to generate driving signals by using input data when a data output enable signal is enabled, a data driver unit configured to drive an output terminal to a level corresponding to the input data in response to the driving signals to generate output data, and an output data level control unit configured to open a current path to control a level of the output data, wherein the current path is different from a current path for driving the output terminal to a level corresponding to the input data.

Abstract: Disclosed are a row addresses control circuit of a semiconductor integrated circuit and method of controlling row addresses using the same. The circuit includes: a pulse generator receiving a bank active signal to generate a bank active pulse signal; a refresh mode input circuit combining the bank active pulse signal with a refresh signal to generate a refresh combination signal; and a plurality of row address control units driving and latching each global row enable signal to convert the global row enable signal to a local row enable signal in response to an input of the refresh combination signal.

Abstract: A skew signal generator is provided which comprises a fuse signal generating unit for generating a plurality of fuse signals, and an encoder for generating skew signals including skew information of a wafer by encoding the fuse signals.

Abstract: A temperature data output circuit is provided which is capable of outputting a temperature signal which is enabled when an internal temperature of at least one of the semiconductor memory chips mounted on a multi chip package exceeds a predetermined temperature.

Abstract: A refresh period signal generator with a digital temperature information generation function includes a temperature information generating part configured to generate temperature information by using a first period signal and a second period signal, a refresh period signal generating part configured to output a refresh period signal by selecting one signal having a shorter period between the first period signal and the second period signal, and an operation timing control part operating the temperature information generating part and the refresh period signal generating part at a predetermined timing.

Abstract: A semiconductor memory apparatus includes a first bank block including a first bank group, a second bank block including a second bank group, and an address control unit that receives an address signal to selectively provide a decoded row address signal to the first bank block or the second bank block in response to a bank address signal.

Abstract: Provided is a pre-driver circuit having a pull-up unit for receiving a data signal, as an input, to output a logical High; a pull-down unit for receiving the data signal, as an input, to output a logical Low; and a control unit for using a control signal reflecting a process completion status to adjust a driving size of the pull-up unit and/or the pull-down unit. According to the present invention, slew of a waveform of an output data can be stably secured regardless of a process condition.

Abstract: An apparatus for controlling an activation of semiconductor integrated circuit includes: an active control unit configured to generate active control signal for determining activation of banks; and a plurality of active signal generating units configured to input the active control signal commonly, and generate active signals for activating the banks to according to the active control signal. According to this structure, it is possible to reduce current consumption to a minimum in a refresh mode, to easily arrange signal lines, and thus to effectively use extra space.

Abstract: In a skew signal generation circuit, a pad is connected to an external resistor and a code generator compares a voltage of the pad with a reference voltage to generate a plurality of codes. A skew signal extractor extracts a skew signal from the codes, the skew signal containing information about a current characteristic of a MOS transistor. A driver calibrates a drivability in response to the skew signal.

Abstract: A circuit for controlling an active period of semiconductor memory apparatus includes: an active controller that generates active control signals for determining active periods of two or more individual banks according to whether a refresh operation is performed; and an active signal generator that generates an active signal for each of the banks so as to correspond to the active control signal. According to this structure, it is possible to reduce current consumption to a minimum in a refresh mode, to easily arrange signal lines, and thus to effectively use extra space.

Abstract: A multichip package in which characteristics of all semiconductor chips mounted thereon can be controlled in response to a change in temperature. The multichip package can include a substrate and a plurality of semiconductor chips that are sequentially stacked and mounted on the substrate. In this case, a temperature detection circuit may be provided on any one of the plurality of semiconductor chips. The semiconductor chips may be electrically connected to the temperature detection circuit that is provided on any one of the plurality of semiconductor chips, and share temperature data that can be obtained from the temperature detection circuit.