Abstract: An off-chip driver circuit including a plurality of delay circuits, at least two of which have different delay times, in which the delay circuits receive a data signal and generate delayed data signals, respectively. The circuit also includes a plurality of off-chip drivers for respectively receiving the delayed data signals from the respective delay circuits and generating respective output signals in response to respective control signals, wherein the total number of the off-chip drivers to be activated at the same time is changed by the respective control signals which are generated in response to a desired drivability, and the activated off-chip drivers sequentially generate the output signals in response to the delay times, thereby increasing a total drivability of the off-chip driver circuit.

Abstract: Disclosed is a circuit for generating pulses for a semiconductor apparatus. The circuit for generating pulses for a semiconductor apparatus includes a temperature sensor, a temperature signal decoder, and a pulse generator. The temperature sensor senses the temperature of a memory chip and converts the temperature into a digital code combination so as to output a plurality of temperature information signals. The temperature signal decoder decodes the plurality of temperature information signals so as to output a delay control signal. The pulse generator outputs an overdriving pulse signal in response to a sense amplifier driving signal and the delay control signal.

Abstract: Disclosed are a row addresses control circuit of a semiconductor integrated circuit and method of controlling row addresses using the same. The circuit includes: a pulse generator receiving a bank active signal to generate a bank active pulse signal; a refresh mode input circuit combining the bank active pulse signal with a refresh signal to generate a refresh combination signal; and a plurality of row address control units driving and latching each global row enable signal to convert the global row enable signal to a local row enable signal in response to an input of the refresh combination signal.

Abstract: Disclosed herein is an internal voltage supply circuit for a semiconductor device. The internal voltage supply circuit includes a first voltage driver for supplying a first voltage in response to a first enable signal, a second voltage driver for supplying a second voltage in response to a second enable signal, and a first enable signal generator for generating the first enable signal having an enable period of a desired time according to a current drive capability of the semiconductor device. The enable period is set to be shorter than a predetermined reference period when the current drive capability of the semiconductor device is higher than a predetermined reference current drive capability, and the enable period is set to be longer than the reference period when the current drive capability of the semiconductor device is lower than the reference current drive capability.

Abstract: An apparatus for controlling operations of a synchronous semiconductor memory device, wherein each operation is achieved by a plurality of internal instructions includes a reference clock block for receiving an external clock and outputting a plurality of delayed clock signals; a control block, in response to the plurality of delayed clock signal, for outputting one of the plurality of internal instructions at a first predetermined timing which is earlier than the timing of starting the operation.

Abstract: A peripheral voltage generator is provided for reducing an operating current by generating a peripheral voltage within a mobile SDRAM, and a current is used in a deep-power down mode and a self refresh mode to thereby enhance operational characteristics. The peripheral voltage generator includes a reference voltage generating unit for generating a peripheral reference voltage having a different level in response to an enable signal and a self-refresh signal; a comparing unit for comparing the peripheral reference voltage with a peripheral driving voltage to thereby output a peripheral voltage control signal based on the comparison result; and a peripheral voltage control unit for generating the peripheral driving voltage having a first peripheral level in response to the peripheral voltage control signal.

Abstract: Disclosed are a semiconductor package device and a method for fabricating the semiconductor package device. The semiconductor package has a semiconductor chip including a plurality of bonding pads having a microscopic size and aligned at a minute interval, a planar layer formed on the semiconductor chip so as to expose the bonding pads, metal patterns formed on the planar layer and having a size larger than a size of the bonding pads in such a manner that at least some parts of the metal patterns are connected to the bonding pads and a seed metal layer interposed between the planar layer and the metal patterns. When the bonding pads have microscopic size and aligned at a minute interval, a wire-bonding process is carried out by using the metal patterns having the size larger than the size of the bonding pads and covering the bonding pad region, as a connection part to the bonding pads. Thus, the bonding pad region is reduced by 50 to 80% so that the number of chips in the semiconductor chip is increased.

Abstract: A circuit for controlling an active period of semiconductor memory apparatus includes: an active controller that generates active control signals for determining active periods of two or more individual banks according to whether a refresh operation is performed; and an active signal generator that generates an active signal for each of the banks so as to correspond to the active control signal. According to this structure, it is possible to reduce current consumption to a minimum in a refresh mode, to easily arrange signal lines, and thus to effectively use extra space.

Abstract: A voltage generator for a peripheral circuit, the voltage generator includes: a voltage supplier supplying a peripheral circuit voltage having a voltage level maintained at a reference voltage level, the peripheral circuit voltage outputted in response to a driving signal; and a voltage level compensator increasing the voltage level of the peripheral circuit voltage in response to a column path command.

Abstract: Provided is a peripheral voltage generator for reducing an operating current by generating a peripheral voltage within a mobile SDRAM, and a current used in a deep-power down mode and a self refresh mode to thereby enhance operational characteristics. The peripheral voltage generator includes a reference voltage generating unit for generating a peripheral reference voltage having a different level in response to an enable signal and a self-refresh signal; a comparing unit for comparing the peripheral reference voltage with a peripheral driving voltage to thereby output a peripheral voltage control signal based on the comparison result; and a peripheral voltage control unit for generating the peripheral driving voltage having a first peripheral level in response to the peripheral voltage control signal.

Abstract: A memory device with an apparatus for recalibrating an output signal of an internal circuit is disclosed. The memory device includes a plurality of signal modulators for simultaneously receiving the output signal of the internal circuit, and a control unit for outputting a control signal for selecting one of the plurality of signal modulators. The control signal output from the control unit includes OCD (Off Chip Driver) calibration information.

Abstract: Disclosed is an input device for a semiconductor device that optimizes the performance characteristic of the semiconductor device using off-chip driver information. The input device includes at least two buffers, connected in parallel to an electrostatic discharge (ESD) circuit, for buffering an input signal applied through the ESD circuit. The buffers have delay times different from each other, one of the buffers is selected using off-chip driver information detected from an output driver and the input signal is transferred through the selected buffer. The signal transfer path of the input device is optionally be selected using the off-chip driver information of the output drivers, and a stable input/output operation of the semiconductor device is achieved even if the performance characteristic of the semiconductor device is changed due to the skew occurring in the fabricating process of the semiconductor device.

Abstract: A memory device capable of reducing power consumption when the operation mode is a deep power down mode, includes an external power source voltage line through which an external power source voltage is supplied; an internal voltage line through which an internal voltage generated in an internal voltage generator is supplied; a ground voltage line through which a ground voltage is supplied; and an internal circuit selectively connected to one of the external power source voltage line, the internal voltage line and the ground line according to the operation modes of the memory device, to use one of the external power source voltage, the internal voltage and the ground voltage as a power source based on the selective connection of the lines.

Abstract: Disclosed herein is an internal voltage supply circuit for a semiconductor device. The internal voltage supply circuit includes a first voltage driver for supplying a first voltage in response to a first enable signal, a second voltage driver for supplying a second voltage in response to a second enable signal, and a first enable signal generator for generating the first enable signal having an enable period of a desired time according to a current drive capability of the semiconductor device. The enable period is set to be shorter than a predetermined reference period when the current drive capability of the semiconductor device is higher than a predetermined reference current drive capability, and the enable period is set to be longer than the reference period when the current drive capability of the semiconductor device is lower than the reference current drive capability.

Abstract: Disclosed are a semiconductor package device and a method for fabricating the semiconductor package device. The semiconductor package has a semiconductor chip including a plurality of bonding pads having a microscopic size and aligned at a minute interval, a planar layer formed on the semiconductor chip so as to expose the bonding pads, metal patterns formed on the planar layer and having a size larger than a size of the bonding pads in such a manner that at least some parts of the metal patterns are connected to the bonding pads and a seed metal layer interposed between the planar layer and the metal patterns. When the bonding pads have microscopic size and aligned at a minute interval, a wire-bonding process is carried out by using the metal patterns having the size larger than the size of the bonding pads and covering the bonding pad region, as a connection part to the bonding pads. Thus, the bonding pad region is reduced by 50 to 80% so that the number of chips in the semiconductor chip is increased.

Abstract: Disclosed are a semiconductor package device and a method for fabricating the semiconductor package device. The semiconductor package has a semiconductor chip including a plurality of bonding pads having a microscopic size and aligned at a minute interval, a planar layer formed on the semiconductor chip so as to expose the bonding pads, metal patterns formed on the planar layer and having a size larger than a size of the bonding pads in such a manner that at least some parts of the metal patterns are connected to the bonding pads and a seed metal layer interposed between the planar layer and the metal patterns. When the bonding pads have microscopic size and aligned at a minute interval, a wire-bonding process is carried out by using the metal patterns having the size larger than the size of the bonding pads and covering the bonding pad region, as a connection part to the bonding pads. Thus, the bonding pad region is reduced by 50 to 80% so that the number of chips in the semiconductor chip is increased.

Abstract: Disclosed is a semiconductor package capable of improving a thermal emission property. The semiconductor package includes a substrate having a window, a first wiring, and a second wiring. A semiconductor chip is attached to the substrate. A metal pattern is formed at a pad-forming surface of the semiconductor chip. A first metal wire connects the bonding pad to a first bond finger and a second metal wire connects the metal pattern to a second bond finger. A sealing member is provided to seal the substrate. A first solder ball is attached to a first ball land and a second solder ball is attached to the second ball land.

Abstract: An apparatus for controlling operations of a synchronous semiconductor memory device, wherein each operation is achieved by a plurality of internal instructions includes a reference clock block for receiving an external clock and outputting a plurality of delayed clock signals; a control block, in response to the plurality of delayed clock signal, for outputting one of the plurality of internal instructions at a first predetermined timing which is earlier than the timing of starting the operation.

Abstract: Disclosed is a semiconductor package capable of reducing thickness of the semiconductor package. The semiconductor package has a first semiconductor chip including a plurality of first bonding pads, a second semiconductor chip aligned adjacent to the first semiconductor chip in the same plane and having a plurality of second bonding pads transferring signals identical to signals transferred by the first bonding pads, planar layers formed on the first and second semiconductor chips and having openings for exposing first and second bonding pads transferring the same signals and metal patterns covering the openings to connect the first bonding pads to the second bonding pads transferring signals identical to signals transferred by the first bonding pads. The semiconductor package is fabricated by connecting adjacent semiconductor chips to each other in the same plane, instead of vertically stacking the semiconductor chips, so that thickness of the semiconductor package is reduced.

Abstract: Disclosed are a semiconductor package device and a method for fabricating the semiconductor package device. The semiconductor package has a semiconductor chip including a plurality of bonding pads having a microscopic size and aligned at a minute interval, a planar layer formed on the semiconductor chip so as to expose the bonding pads, metal patterns formed on the planar layer and having a size larger than a size of the bonding pads in such a manner that at least some parts of the metal patterns are connected to the bonding pads and a seed metal layer interposed between the planar layer and the metal patterns. When the bonding pads have microscopic size and aligned at a minute interval, a wire-bonding process is carried out by using the metal patterns having the size larger than the size of the bonding pads and covering the bonding pad region, as a connection part to the bonding pads. Thus, the bonding pad region is reduced by 50 to 80% so that the number of chips in the semiconductor chip is increased.