Patents by Inventor Ho-Young Son

Ho-Young Son has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070259515
    Abstract: The present invention provides a method for manufacturing a wafer-level package comprising the steps of coating adhesives on a wafer on which bumps are already formed and irradiating the adhesive layer using a laser to divide the wafer into individual chip units. According to the present invention, it is possible to effectively prevent adhesives from absorbing water during the dicing process when manufacturing a wafer-level package.
    Type: Application
    Filed: May 3, 2007
    Publication date: November 8, 2007
    Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Kyung-Wook Paik, Ho-Young Son
  • Publication number: 20070054419
    Abstract: Disclosed is a wafer level chip size package for an image sensor module and a manufacturing method thereof, more particularly to a small size image sensor module characterized by a structure where a glass formed with an I/R cut-off filter (layer) is assembled onto an image sensor chip by a polymer partition wall and a solder bump is formed on an electrode of the rear side of a chip connected by a through-hole formed on each I/O electrode of an image sensor chip and a wafer level chip size package process for realizing the module. The method for manufacturing a wafer level chip size package for an image sensor module, the method comprises: bonding an image sensor wafer glass and a glass wafer to form a through-hole on the image sensor wafer; filling the through-hole formed on the image sensor wafer with an exciting material; and forming a solder bump at the end of the exciting material to be connected with the circuit formed PCB substrate.
    Type: Application
    Filed: August 31, 2006
    Publication date: March 8, 2007
    Inventors: Kyung-Wook Paik, Myung-Jin Yim, Ho-Young Son
  • Publication number: 20060252246
    Abstract: The present invention relates to an image sensor module and a manufacturing method thereof, especially to a wafer level chip size package (WL-CSP) realized by directly contacting an image sensor chip wafer to a glass wafer on which an IR filter coating layer is deposited, an electrode rearrangement and a dicing process, a miniaturized image sensor module using this wafer level chip size package (WL-CSP) and a method thereof. The CMOS image sensor module using a wafer level chip size package technology according to the present invention comprises: an image sensor chip wafer having a partition with a lattice structure formed at portions except an image sensing area; and a glass wafer with an IR filter coating layer and a metal electrode; and wherein the image sensor chip wafer and the glass wafer form an electric contact and a chip sealing by a flip-chip bonding; and wherein a solder bump and a non solder bump are formed after a metal wiring is rearranged on a lower surface of the glass wafer.
    Type: Application
    Filed: April 3, 2006
    Publication date: November 9, 2006
    Inventors: Kyung-Wook Paik, Myung-Jin Yim, Ho-Young Son, Yong-Min Kwon