Abstract: A method for fabricating a guard ring structure for JFETs and MESFETs. Trenches are etched in a semiconductor substrate for fabrication of a gate structure for a JFET or MESFET. At time the gate trenches are etched, concentric guard ring trenches are also etched. The process used to fabricate the gate p-h junction or Schottky barrier at the bottom of the gate trenches is also used to fabricate the guard ring at bottom of the guard ring trenches. The separation between the guard ring trenches is 1.0 to 3.0 times greater than the separation between the gate trenches.

Abstract: A protection device for integrated circuits. A complementary well is fabricated in a semiconductor substrate. An enhancement mode junction field effect transistor (JFET) is fabricated in the complementary well. An interface bonding pad is fabricated above the JFET. A source contact is also fabricated in the well. The gate and drain of the JFET are coupled to the interface bonding pad and the source of the JFET is coupled to the substrate.

Abstract: A method for fabricating a junction field effect transistor (JFET) with a double dose gate structure. A trench is etched in the surface of a semiconductor substrate, followed by a low dose implant to form a first gate region. An anneal may or may not be performed after the low dose implant. A gate definition spacer is then formed on the wall the trench to establish the lateral extent of a second, high dose implant gate region. After the second implant, the gate is annealed. The double dose gate structure produced by the superposition of two different and overlapping regions provides an additional degree of flexibility in determining the ultimate gate region doping profile. A further step comprises using the gate definition spacer to define the walls of a second etched trench that is used to remove a portion of the p-n junction, thereby further reducing the junction capacitance.

Abstract: A semiconductor switching device or amplifier combined in parallel with one or more active devices defined as starter devices. A starter device is used to reduce the terminal voltage of a switching device or amplifier to a dc level below about 0.4 volts which will then allow the switching device to easily change between the on or conducting state and the off or non-conducting state. Three different starter devices are utilized. The first being a Bipolar Junction Transistor (BJT), the second a Metal Oxide Silicon Field Effect Transistor (MOSFET), and the third consisting of three normally off JFETs connected serially. Generally, a single starter device is coupled across the terminals of a semiconductor switching device or amplifier, but it is possible and sometimes advantageous to couple two or more starter devices in parallel. In a first case, a symmetrical, normally off or enhancement mode JFET is used as the switch or amplifier.

Abstract: JFET and MESFET structures, and processes of making same, for low voltage, high current and high frequency applications. The structures may be used in normally-on (e.g., depletion mode) or normally-off modes. The structures include an oxide layer positioned under the gate region which effectively reduces the junction capacitance (gate to drain) of the structure. For normally off modes, the structures reduce gate current at Vg in forward bias. In one embodiment, a silicide is positioned in part of the gate to reduce gate resistance. The structures are also characterized in that they have a thin gate due to the dipping of the spacer oxide, which can be below 1000 angstroms and this results in fast switching speeds for high frequency applications.

Abstract: A method for fabricating a junction field transistor for high-voltage applications. A lightly doped first epitaxial layer is formed on a highly doped substrate. A second epitaxial layer is deposited with a heavier dopant concentration than the first epitaxial layer. The second layer contains a control structure having a plurality of implanted gate regions and a source. A guard ring is formed to isolate the source and the control structure. The combination of the lightly doped first epitaxial layer and the guard ring enable the JFET to be operated with a breakdown voltage in excess of 100 volts. Multiple guard rings may be used to provide a breakdown voltage in excess of 150 volts.

Abstract: A method and structure for a composite trench fill for silicon electronic devices. On a planar silicon substrate having a first deposited layer of oxide and a second deposited layer of polysilicon, a trench is etched. Deposition and etch processes using a combination of oxide and polysilicon are used to fabricate a composite trench fill. The trench bottom and a lower portion of the walls are covered with oxide. The remaining portion of the trench volume is filled with polysilicon. The method may be used for junction field effect transistors (JFETs) and metal oxide semiconductor field effect transistors (MOSFETs).

Abstract: A method for fabricating a junction field effect transistor (JFET) with a double dose gate structure. A trench is etched in the surface of a semiconductor substrate, followed by a low dose implant to form a first gate region. An anneal may or may not be performed after the low dose implant. A gate definition spacer is then formed on the wall the trench to establish the lateral extent of a second, high dose implant gate region. After the second implant, the gate is annealed. The double dose gate structure produced by the superposition of two different and overlapping regions provides an additional degree of flexibility in determining the ultimate gate region doping profile. A further step comprises using the gate definition spacer to define the walls of a second etched trench that is used to remove a portion of the p-n junction, thereby further reducing the junction capacitance.

Abstract: A protection device for integrated circuits. A complementary well is fabricated in a semiconductor substrate. An enhancement mode junction field effect transistor (JFET) is fabricated in the complementary well. An interface bonding pad is fabricated above the JFET. A source contact is also fabricated in the well. The gate and drain of the JFET are coupled to the interface bonding pad and the source of the JFET is coupled to the substrate.

Abstract: The present invention relates generally to electrical cascade circuits using normally-off junction field effect transistors (JFETs) which have low on-resistance for low voltage and high current density applications. Proper configuration of the normally-off JFETs allows for low voltage drop, low-on resistance, high current density and high frequency operations. More particularly, these cascade circuits are configured to provide amplification of an input signal and signal switching capabilities. In general two or more normally-off JFETs are coupled together on a substrate to create a desired characteristic. For a three terminal gate-controlled cascade amplification circuit, an input signal at the first JFET can realize a signal gain of 80 dB to 120 dB at the second JFET. A four terminal gate-controlled cascade switching circuit, comprised of two JFETs, switches on or off to regulate current flow through the second JFET.

Abstract: A two terminal semiconductor circuit that can be used to replace the semiconductor diodes used as rectifiers in conventional DC power supply circuits. Three semiconductor circuits that can efficiently supply the DC currents required in both discrete and integrated circuits being operated at low DC supply voltages are disclosed. All three circuits have a forward or current conducting state and a reverse or non current conducting state similar to a conventional semiconductor diode.

Abstract: A normally “off” enhancement mode junction field effect transistor (JFET) is disclose. The JFET has a low threshold voltage in the range of 0.2 to 0.3 volts and a low on resistance. The Drain-to-Source voltage drop is less than 0.1 volt at a drain current of 100 amperes.

Abstract: This invention discloses rectifying circuits using normally “off” Junction Effect Transistor. By connecting the gate of the JFET to the higher bias terminal of the output coil of the transformer, the forward biased turn on function of the normally “off” JFETs can be achieved. Therefore, the normally “off” JFET can be used as synchronized zero voltage switching rectifier with very low voltage drop. Since normally “off” JFET is a majority carrier device, very high frequency response can be achieved. This kind of circuitry can replace the P-N junction and/or Schottky rectifiers especially when the supply voltage drops below three volts.

Abstract: A semiconductor switching device or amplifier combined in parallel with one or more active devices defined as starter devices. A starter device is used to reduce the terminal voltage of a switching device or amplifier to a dc level below about 0.4 volts which will then allow the switching device to easily change between the on or conducting state and the off or non-conducting state. Three different starter devices are utilized. The first being a Bipolar Junction Transistor (BJT), the second a Metal Oxide Silicon Field Effect Transistor (MOSFET), and the third consisting of three normally off JFETs connected serially. Generally, a single starter device is coupled across the terminals of a semiconductor switching device or amplifier, but it is possible and sometimes advantageous to couple two or more starter devices in parallel. In a first case, a symmetrical, normally off or enhancement mode JFET is used as the switch or amplifier.

Abstract: An enhancement mode JFET as a switching device in a boost converter circuit combined with a single rectifier diode and an inductor. A control circuit coupled to the gate of the JFET switches the JFET between a current conducting state and a current blocking state. The ratio of converter dc output voltage to converter dc input voltage is determined by the ratio of JFET conducting time to the sum of JFET conducting time and JFET blocking time. This pulse width modulation scheme is thus used to adjust the dc output voltage level. Limits on both frequency of operation and duty cycle result from slow switching speeds. Each time a device switches between states, a certain amount of energy is lost. The slower the device switching time, the greater the power loss in the circuit. The effects become very important in high frequency (fast switching) and/or high power circuits where as much as 50% of the losses are due to excessive switch transition time.

Abstract: A two terminal semiconductor circuit that can be used to replace the semiconductor diodes used as rectifiers in conventional DC power supply circuits. Three semiconductor circuits that can efficiently supply the DC currents required in both discrete and integrated circuits being operated at low DC supply voltages are disclosed. All three circuits have a forward or current conducting state and a reverse or non current conducting state similar to a conventional semiconductor diode. In a first configuration, an asymmetrical, enhancement mode, Junction Field Effect Transistor (JFET) is utilized as a two terminal device by connecting together the gate and source leads. The terminal voltage in the conducting state is considerably smaller than conventional semiconductor diodes. In a second configuration, an asymmetrical, enhancement mode, Junction Field Effect Transistor (JFET) is connected with a transformer such that the source and the drain serve as the two leads of a two terminal circuit.

Abstract: A four terminal full wave rectifier circuit that can be used as a pin for pin replacement for the full wave diode rectifier circuit commonly used in DC power supply circuits. Two full wave rectifier circuits that can efficiently supply the DC currents required in both discrete and integrated circuits being operated at low DC supply voltages are disclosed. Both circuits utilize two n-channel, enhancement mode Junction Field Effect Transistors (JFET) and two p-channel, enhancement mode Junction Field Effect Transistors to replace the rectifier diodes used in a conventional full wave rectifier circuit. The forward voltage drop across each JFET is considerably smaller than the forward voltage drop of a conventional rectifier. In a first configuration, the JFETs are all symmetrical about the source and drain leads. Starter devices are connected between source and drain leads and current limiting devices are in series with the gate leads.

Abstract: This invention discloses the concept of the integration of the four terminal switcher and the capacitor pairs for the DC to DC converter or power supplier. This invention can be built by IC process as the DC to DC converter or power supply alone or used as power supply or converter module or block for distributed power in the System-on-Chip. This invention discloses the basic structure of the DC to DC converter or power supply module on standard CMOS IC process and on SOI substrates. This basic structure of the DC to DC converter or power supply module provides high current and low voltage applications for future generations of ICs.

Abstract: This invention discloses the present invention discloses a junction field effect transistor (JFET) device supported on a substrate. The JFET device includes a gate surrounded by a depletion region. As the distance between the gates is large enough, there is a gap between the depletion regions surrounding adjacent gates. Depletion mode JFET transistor which is normally on is provided. The normally on transistors respond to negative bias applied to the gates to shut of the current path in the substrate. The current path in the substrate is normally available with a zero gate bias. As the distance between the gates is reduced, the JFET transistor is normally off because the depletion regions surround the gates shut of the current channel. The depletion region responding to a positive bias applied to the gate to open a current path in the substrate wherein the current path in the substrate is shut off when the gate is zero biased.

Abstract: An enhancement mode JFET as a switching device in a buck converter circuit combined with a single rectifier diode and an inductor. A control circuit coupled to the gate of the JFET switches the JFET between a current conducting state and a current blocking state. The ratio of converter dc output voltage to converter dc input voltage is determined by the ratio of JFET conducting time to the sum of JFET conducting time and JFET blocking time. This pulse width modulation scheme is thus used to adjust the dc output voltage level. Limits on both frequency of operation and duty cycle result from slow switching speeds. Each time a device switches between states, a certain amount of energy is lost. The slower the device switching time, the greater the power loss in the circuit. The effects become very important in high frequency (fast switching) and/or high power circuits where as much as 50% of the losses are due to excessive switch transition time.