Abstract: A semiconductor device efficiently providing the DC currents required in both discrete and integrated circuits operated at low DC supply voltages. The device disclosed in the present invention is an asymmetrical, enhancement mode, Junction Field Effect Transistor (JFET). The device consists of an epitaxial layer on the surface of a substrate, both of which are doped with the same polarity. The epitaxial layer has a graded doping profile with doping density increasing with distance from the substrate. A grill-like structure is constructed within the upper and lower bounds of, and extending throughout the length and width of the epitaxial layer, and is doped with a polarity opposite to that of the epitaxial layer. A first electrical connection made to the exposed side of the substrate is defined as the drain electrode. A second electrical connection made to the exposed surface of the epitaxial layer is defined as the source electrode.

Abstract: A four terminal full wave rectifier circuit that can be used as a pin for pin replacement for the full wave diode rectifier circuit commonly used in DC power supply circuits. Two full wave rectifier circuits that can efficiently supply the DC currents required in both discrete and integrated circuits being operated at low DC supply voltages are disclosed. Both circuits utilize two n-channel, enhancement mode Junction Field Effect Transistors (JFET) and two p-channel, enhancement mode Junction Field Effect Transistors to replace the rectifier diodes used in a conventional full wave rectifier circuit. The forward voltage drop across each JFET is considerably smaller than the forward voltage drop of a conventional rectifier. In a first configuration, the JFETs are all symmetrical about the source and drain leads. Starter devices are connected between source and drain leads and current limiting devices are in series with the gate leads.

Abstract: This invention discloses a wafer level packaging method and configuration. This improved wafer level package includes a processed wafer mounted on a first printed circuit board (PCB) carrier. The processed wafer mounted on the PCB carrier board includes a plurality of separated integrated circuit (IC) chips divided by scribe-line gaps wherein each of these scribe-line gaps is filled with flexible gap-filling insulation material. In another preferred embodiment, the wafer-level package further includes a second PCB carried board composed of same material as the first PCB carrier board mounted on top of the wafer. In another preferred embodiment, the wafer-level package, which having the first and the second PCB carrier boards further includes a plurality of connection via penetrating through the first and the second PCB carried board for forming electric connection to the IC chips separated by the scribe-line gaps.

Abstract: Junction Field Effect Transistor (JFET) offers fast switching speed than bipolar transistor since JFET is a majority carrier device. This invention comprises two normally “off” JFETs, one in N-channel and one in P-channel to form Complementary Junction Field Effect Transistors for high speed, low voltage and/or high current applications. The discrete device structure is disclosed in this invention. The integrated Complementary Junction Field Effect Transistors structure processed in standard CMOS process is disclosed in this invention. A vertical gate structure of Complementary Junction Field Effect Transistors is disclosed. Complementary Junction Field Effect Transistors structure is also disclosed in SOI substrate.

Abstract: This invention discloses a switching device that switches an array of capacitors in series configuration in charging condition and switches an array of capacitors in parallel configuration in discharging condition for voltage stepdown DC to DC converter. This switcher can also be used for the voltage stepup conversion by charging an array of capacitors in the parallel configuration and discharging an array of capacitors in series configuration. The novel structure of this invention is to use the normally “offs” JFETs with both N-chamel and P-channel that provide low on resistance of sub-milliohm and large current for high efficiency energy conversions. This invention discloses the integrated structure of the switcher. The switcher built in common CMOS IC process is also disclosed in this invention.

Abstract: This invention discloses the concept of the integration of the four terminal switcher and the capacitor pairs for the DC to DC converter or power supplier. This invention can be built by IC process as the DC to DC converter or power supply alone or used as power supply or converter module or block for distributed power in the System-on-Chip. This invention discloses the basic structure of the DC to DC converter or power supply module on standard CMOS IC process and on SOI substrates. This basic structure of the DC to DC converter or power supply module provides high current and low voltage applications for future generations of ICs.

Abstract: This invention discloses the present invention discloses a junction field effect transistor UFET) device supported on a substrate. The JFET device includes a gate surrounded by a depletion region. As the distance between the gates is large enough, there is a gap between the depletion regions surrounding adjacent gates. Depletion mode JFET transistor which is normally on is provided. The normally on transistors respond to negative bias applied to the gates to shut of the current path in the substrate. The current path in the substrate is normally available with a zero gate bias. As the distance between the gates is reduced, the JFET transistor is normally off because the depletion regions surround the gates shut of the current channel. The depletion region responding to a positive bias applied to the gate to open a current path in the substrate wherein the current path in the substrate is shut off when the gate is zero biased.

Abstract: This invention discloses a Schottky barrier rectifier formed in a semiconductor chip of a first conductivity type having a cathode electrode connected thereto near a bottom surface of the semiconductor chip. The Schottky rectifier further includes an epitaxial layer of the first conductivity type of a reduced doping concentration than the semiconductor chip near a top surface of the semiconductor chip. The Schottky rectifier further includes a high resistivity region disposed near peripheral edges of the semiconductor chip containing a reduced dopant concentration than the epitaxial layer. The Schottky rectifier further includes an anode electrode defined by a conductive layer disposed on top over the epitaxial layer wherein the conductive layer having all peripheral edges disposed on top of the high resistivity region. In a preferred embodiment, e.g.

Abstract: A rechargeable battery pack which includes several battery cells. Each cell has a positive electrode and a negative electrode connected in series. Each of the battery cells further includes a reverse polarity protection device. The protection device includes a low voltage switch connected between the positive electrode and the negative electrode of the battery cell. The low voltage switch is switched on to become a short circuit when a voltage difference between the positive electrode and the negative electrode for each of the battery cells is lower than a threshold switch-on voltage such that the each of the battery cells is bypassed and protected by conducting a current through the short circuit in the low voltage switch.

Abstract: A bipolar transistor is fabricated in a CMOS-compatible process so as to be self-aligning, with resultant small geometry and improved high frequency performance, and to have improved hot carrier characteristics. The bipolar device has a laterally graded emitter structure that is fabricated in a "top-down" implant process. During fabrication sidewall spacers are formed overlying the peripheral region of the laterally graded emitter. These spacers protect the underlying region against counter-doping during a subsequent intrinsic base implant, and cause the emitter and base contacts to be self-aligning. Because bipolar dimensions are thus reduced, a very narrow base width is achieved, resulting in improved device cutoff frequency. Further, a narrower emitter-base contact separation is achieved, reducing junction area and attendant junction capacitance. A base link region is formed to further improve emitter-base breakdown voltage, and to reduce extrinsic base resistance.