Patents by Inventor Ho-Yung David Hwang
Ho-Yung David Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10410921Abstract: A first metallization layer comprising a set of first conductive lines that extend along a first direction on a first insulating layer on a substrate. A second insulating layer is on the first insulating layer. A second metallization layer comprises a set of second conductive lines on a third insulating layer and on the second insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. A via between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines.Type: GrantFiled: February 11, 2019Date of Patent: September 10, 2019Assignee: Micromaterials LLCInventors: Ying Zhang, Abhijit Basu Mallick, Regina Freed, Nitin K. Ingle, Uday Mitra, Ho-yung David Hwang
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Publication number: 20190189512Abstract: A first metallization layer comprising a set of first conductive lines that extend along a first direction on a first insulating layer on a substrate. A second insulating layer is on the first insulating layer. A second metallization layer comprises a set of second conductive lines on a third insulating layer and on the second insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. A via between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines.Type: ApplicationFiled: February 11, 2019Publication date: June 20, 2019Inventors: Ying Zhang, Abhijit Basu Mallick, Regina Freed, Nitin K. Ingle, Uday Mitra, Ho-yung David Hwang
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Publication number: 20190189510Abstract: Methods of forming a self-aligned via comprising recessing a first metallization layer comprising a set of first conductive lines that extend along a first direction on a first insulating layer on a substrate. A second insulating layer is formed on the first insulating layer. A via is formed through the second insulating layer to one of the first conductive lines. Semiconductor devices comprising the self-aligned via and apparatus for forming the self-aligned via are also disclosed.Type: ApplicationFiled: December 11, 2018Publication date: June 20, 2019Inventors: Yung-Chen Lin, Qingjun Zhou, Ying Zhang, Ho-yung David Hwang, Uday Mitra, Regina Freed
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Patent number: 10274839Abstract: A method for controlling semiconductor production through use of a Focus Exposure Matrix (FEM) model includes taking measurements of characteristics of a two-dimensional mark formed onto a substrate, the two-dimensional mark including two different patterns along two different cut-lines, and comparing the measurements with a FEM model to determine focus and exposure conditions used to form the two-dimensional mark. The FEM model was created using measurements taken of corresponding two-dimensional marks formed onto a substrate under varying focus and exposure conditions.Type: GrantFiled: May 24, 2013Date of Patent: April 30, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Zhan Zhou, Heng-Jen Lee, Chen-Ming Wang, Kai-Hsiung Cheng, Chih-Ming Ke, Ho-Yung David Hwang
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Publication number: 20190067102Abstract: Methods and apparatus to form fully self-aligned vias are described. A first metal film is formed in the recessed first conductive lines and on the first insulating layer of a substrate comprising alternating conductive lines and a first insulating layer. Pillars and a sheet are formed from the first metal film. Some of the pillars and a portion of the sheet are selectively removed and a second insulating layer is deposited around the remaining pillars and sheet. The remaining pillars and sheet are removed to form vias and a trench in the second insulating layer. A third insulating layer is deposited in the vias and trench and an overburden is formed on the second insulating layer. Portions of the overburden are selectively etched from the second insulating layer to expose the second insulating layer and the filled vias and leaving portions of the third insulating layer on the second insulating layer.Type: ApplicationFiled: August 29, 2018Publication date: February 28, 2019Inventors: Ying Zhang, Abhijit Basu Mallick, Yung-Chen Lin, Qingjun Zhou, He Ren, Ho-yung David Hwang, Uday Mitra
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Publication number: 20180306514Abstract: A method includes supporting a wafer on a heating element, wherein the heating element is located in a baking chamber. The method further includes heating the wafer for a first duration using the heating element. The method further includes measuring a temperature of the heating element and a temperature of the wafer during the first duration to obtain temperature information. The method further includes adjusting an amount of heat provided by the heating element during the first duration, wherein the adjusting of the amount of heat includes decreasing the amount of heat provided by the heating element as a rate of change of the temperature information versus time increases.Type: ApplicationFiled: June 25, 2018Publication date: October 25, 2018Inventors: Tzung-Chen WU, Wen-Zhan ZHOU, Heng-Jen LEE, Ho-Yung David HWANG
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Patent number: 10006717Abstract: An adaptive baking system includes a baking chamber configured to receive a wafer, and a heating element configured to support the wafer. The adaptive baking system further includes a controller configured to receive temperature information related to the heating element and the wafer, wherein the controller is further configured to adjust an amount of heat provided by the heating element during a baking process in response to the temperature information.Type: GrantFiled: March 7, 2014Date of Patent: June 26, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzung-Chen Wu, Wen-Zhan Zhou, Heng-Jen Lee, Ho-Yung David Hwang
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Publication number: 20180067395Abstract: A photolithography system includes a variable-volume buffer tank, a dispensing system connected to the buffer tank, and a valve configured to release gas from a head space of the buffer tank while blocking the release of liquid from the head space. A storage container has an opening at the bottom and drains to the buffer tank through that opening. The buffer tank has a storage capacity sufficient to receive the full contents of the storage container. The system supplies chemical solutions to the dispensing system while keeping the chemical solutions from contact with air and other gases.Type: ApplicationFiled: November 8, 2017Publication date: March 8, 2018Inventors: Wen-Zhan Zhou, Heng-Jen Lee, Hsu-Yuan Liu, Yu-Chen Huang, Cheng-Han Wu, Shih-Che Wang, Ho-Yung David Hwang
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Patent number: 9817315Abstract: A photolithography system includes a variable-volume buffer tank, a dispensing system connected to the buffer tank, and a valve configured to release gas from a head space of the buffer tank while blocking the release of liquid from the head space. A storage container has an opening at the bottom and drains to the buffer tank through that opening. The buffer tank has a storage capacity sufficient to receive the full contents of the storage container. The system supplies chemical solutions to the dispensing system while keeping the chemical solutions from contact with air and other gases.Type: GrantFiled: March 13, 2014Date of Patent: November 14, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Zhan Zhou, Heng-Jen Lee, Hsu-Yuan Liu, Yu-Chen Huang, Cheng-Han Wu, Shih-Che Wang, Ho-Yung David Hwang
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Patent number: 9690212Abstract: A method for controlling semiconductor production through use of a hybrid Focus Exposure Matrix (FEM) model includes taking measurements of a set of structures formed onto a substrate. The method further includes using a FEM model to determine focus and exposure conditions used to form the structure The model was created through use of measurements of structures formed on a substrate under varying focus and exposure conditions, the measurements being taken using both an optical measurement tool and a scanning electron microscope.Type: GrantFiled: May 24, 2013Date of Patent: June 27, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Zhan Zhou, Heng-Jen Lee, Yen-Liang Chen, Kai-Hsiung Chen, Chih-Ming Ke, Ho-Yung David Hwang
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Patent number: 9153435Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon (111) surface. The method includes forming a high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate. The high CTE layer has a CTE greater than the CTE of silicon. The method includes forming a buffer layer over the second side of the silicon substrate. The buffer layer has a CTE greater than the CTE of silicon. The method includes forming a III-V family layer over the buffer layer. The III-V family layer has a CTE greater than the CTE of the buffer layer.Type: GrantFiled: May 12, 2014Date of Patent: October 6, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Ming Chen, Chung-Yi Yu, Chia-Shiung Tsai, Ho-Yung David Hwang
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Publication number: 20150261089Abstract: A photolithography system includes a variable-volume buffer tank, a dispensing system connected to the buffer tank, and a valve configured to release gas from a head space of the buffer tank while blocking the release of liquid from the head space. A storage container has an opening at the bottom and drains to the buffer tank through that opening. The buffer tank has a storage capacity sufficient to receive the full contents of the storage container. The system supplies chemical solutions to the dispensing system while keeping the chemical solutions from contact with air and other gases.Type: ApplicationFiled: March 13, 2014Publication date: September 17, 2015Inventors: Wen-Zhan Zhou, Heng-Jen Lee, Hsu-Yuan Liu, Yu-Chen Huang, Cheng-Han Wu, Shih-Che Wang, Ho-Yung David Hwang
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Publication number: 20150253083Abstract: An adaptive baking system includes a baking chamber configured to receive a wafer, and a heating element configured to support the wafer. The adaptive baking system further includes a controller configured to receive temperature information related to the heating element and the wafer, wherein the controller is further configured to adjust an amount of heat provided by the heating element during a baking process in response to the temperature information.Type: ApplicationFiled: March 7, 2014Publication date: September 10, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMAPNY, LTD.Inventors: Tzung-Chen WU, Wen-Zhan ZHOU, Heng-Jen LEE, Ho-Yung David HWANG
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Patent number: 9123671Abstract: Provided is a method of fabricating a semiconductor device. The method includes: receiving a silicon wafer that contains oxygen; forming a zone in the silicon wafer, the zone being substantially depleted of oxygen; causing a nucleation process to take place in the silicon wafer to form oxygen nuclei in a region of the silicon wafer outside the zone; and growing the oxygen nuclei into defects. Also provided is an apparatus that includes a silicon wafer. The silicon wafer includes: a first portion that is substantially free of oxygen, the first portion being disposed near a surface of the silicon wafer; and a second portion that contains oxygen; wherein the second portion is at least partially surrounded by the first portion.Type: GrantFiled: December 30, 2010Date of Patent: September 1, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Ming Chen, Chung-Yi Yu, Chia-Shiung Tsai, Ho-Yung David Hwang, Alexander Kalnitsky
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Publication number: 20140253901Abstract: A method for controlling semiconductor production through use of a Focus Exposure Matrix (FEM) model includes taking measurements of characteristics of a two-dimensional mark formed onto a substrate, the two-dimensional mark including two different patterns along two different cut-lines, and comparing the measurements with a FEM model to determine focus and exposure conditions used to form the two-dimensional mark. The FEM model was created using measurements taken of corresponding two-dimensional marks formed onto a substrate under varying focus and exposure conditions.Type: ApplicationFiled: May 24, 2013Publication date: September 11, 2014Inventors: Wen-Zhan Zhou, Heng-Jen Lee, Chen-Ming Wang, Kai-Hsiung Cheng, Chih-Ming Ke, Ho-Yung David Hwang
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Publication number: 20140257761Abstract: A method for controlling semiconductor production through use of a hybrid Focus Exposure Matrix (FEM) model includes taking measurements of a set of structures formed onto a substrate. The method further includes using a FEM model to determine focus and exposure conditions used to form the structure The model was created through use of measurements of structures formed on a substrate under varying focus and exposure conditions, the measurements being taken using both an optical measurement tool and a scanning electron microscope.Type: ApplicationFiled: May 24, 2013Publication date: September 11, 2014Inventors: Wen-Zhan Zhou, Heng-Jen Lee, Yen-Liang Chen, Kai-Hsiung Chen, Chih-Ming Ke, Ho-Yung David Hwang
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Publication number: 20140242759Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon (111) surface. The method includes forming a high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate. The high CTE layer has a CTE greater than the CTE of silicon. The method includes forming a buffer layer over the second side of the silicon substrate. The buffer layer has a CTE greater than the CTE of silicon. The method includes forming a III-V family layer over the buffer layer. The III-V family layer has a CTE greater than the CTE of the buffer layer.Type: ApplicationFiled: May 12, 2014Publication date: August 28, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Ming Chen, Chung-Yi Yu, Chia-Shiung Tsai, Ho-Yung David Hwang
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Publication number: 20140242768Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon (111) surface. The method includes forming a high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate. The high CTE layer has a CTE greater than the CTE of silicon. The method includes forming a buffer layer over the second side of the silicon substrate. The buffer layer has a CTE greater than the CTE of silicon. The method includes forming a III-V family layer over the buffer layer. The III-V family layer has a CTE greater than the CTE of the buffer layer.Type: ApplicationFiled: May 12, 2014Publication date: August 28, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Ming Chen, Chung-Yi Yu, Chia-Shiung Tsai, Ho-Yung David Hwang
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Patent number: 8791504Abstract: A circuit structure includes a substrate, a nucleation layer of undoped aluminum nitride, a graded buffer layer comprising aluminum, gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant, a ungraded buffer layer comprising gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant without aluminum, and a bulk layer of undoped gallium nitride over the ungraded buffer layer. The various dopants in the graded buffer layer and the ungraded buffer layer increases resistivity and results in layers having an intrinsically balanced conductivity.Type: GrantFiled: October 20, 2011Date of Patent: July 29, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Ming Chen, Po-Chun Liu, Hung-Ta Lin, Chin-Cheng Chang, Chung-Yi Yu, Chia-Shiung Tsai, Ho-Yung David Hwang
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Patent number: 8772831Abstract: A circuit structure includes a substrate and a patterned dielectric layer over the substrate. The patterned dielectric layer includes a plurality of vias; and a number of group-III group-V (III-V) compound semiconductor layer. The III-V compound semiconductor layers include a first layer in the vias, a second layer over the first layer and the dielectric layer, and a bulk layer over the second layer.Type: GrantFiled: November 7, 2011Date of Patent: July 8, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Ming Chen, Po-Chun Liu, Hung-Ta Lin, Chin-Cheng Chang, Chung-Yi Yu, Chia-Shiung Tsai, Ho-Yung David Hwang