Patents by Inventor Ho-geon Song
Ho-geon Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11495576Abstract: A semiconductor package includes a first die including a signal region and a peripheral region bordering the signal region and having first vias in the peripheral region, a second die stacked on the first die and having second vias at positions corresponding to the first vias in the peripheral region, and first connection terminals between the first die and the second die that are configured to connect the second vias to the first vias, respectively. The peripheral region includes first regions and second regions configured to transmit different signals, which are alternately arranged in a first direction. The first vias are arranged in at least two rows along a second direction intersecting the first direction in each of the first and second regions.Type: GrantFiled: March 18, 2020Date of Patent: November 8, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyoungsoo Kim, Sunwon Kang, Seungduk Baek, Ho Geon Song, Kyung Suk Oh
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Patent number: 10896879Abstract: A semiconductor package includes a semiconductor package substrate. An insulating layer is disposed on the semiconductor package substrate. A semiconductor chip is disposed on the semiconductor package substrate and is covered by the insulating layer. A reflective layer is disposed on the insulating layer and is spaced apart from the semiconductor chip. The reflective layer is configured to selectively transmit radiation through to the insulating layer. A protective layer is disposed on the reflective layer.Type: GrantFiled: November 27, 2018Date of Patent: January 19, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kun Sil Lee, Dong Kwan Kim, Bo Ram Kang, Ho Geon Song, Won Keun Kim
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Publication number: 20210005576Abstract: A semiconductor package includes a first die including a signal region and a peripheral region bordering the signal region and having first vias in the peripheral region, a second die stacked on the first die and having second vias at positions corresponding to the first vias in the peripheral region, and first connection terminals between the first die and the second die that are configured to connect the second vias to the first vias, respectively. The peripheral region includes first regions and second regions configured to transmit different signals, which are alternately arranged in a first direction. The first vias are arranged in at least two rows along a second direction intersecting the first direction in each of the first and second regions.Type: ApplicationFiled: March 18, 2020Publication date: January 7, 2021Inventors: Kyoungsoo Kim, Sunwon Kang, Seungduk Baek, Ho Geon Song, Kyung Suk Oh
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Patent number: 10756062Abstract: A semiconductor chip includes a semiconductor substrate, a through electrode, an inter-mediation pad, an upper pad, and a rewiring line. The semiconductor substrate includes a first surface that is an active surface and a second surface that is opposite to the first surface. The through electrode penetrates the semiconductor substrate and is disposed in at least one column in a first direction in a center portion of the semiconductor substrate. The inter-mediation pad is disposed in at least one column in the first direction in an edge portion of the second surface. The upper pad is disposed on the second surface and connected to the through electrode. The rewiring line is disposed on the second surface and connects the inter-mediation pad to the upper pad.Type: GrantFiled: March 20, 2019Date of Patent: August 25, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyoung-Soo Kim, Seung-Duk Baek, Sun-Won Kang, Ho-Geon Song, Gun-Ho Chang
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Publication number: 20200013753Abstract: A semiconductor chip includes a semiconductor substrate, a through electrode, an inter-mediation pad, an upper pad, and a rewiring line. The semiconductor substrate includes a first surface that is an active surface and a second surface that is opposite to the first surface. The through electrode penetrates the semiconductor substrate and is disposed in at least one column in a first direction in a center portion of the semiconductor substrate. The inter-mediation pad is disposed in at least one column in the first direction in an edge portion of the second surface. The upper pad is disposed on the second surface and connected to the through electrode. The rewiring line is disposed on the second surface and connects the inter-mediation pad to the upper pad.Type: ApplicationFiled: March 20, 2019Publication date: January 9, 2020Inventors: Kyoung-Soo Kim, Seung-Duk Baek, Sun-Won Kang, Ho-Geon Song, Gun-Ho Chang
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Publication number: 20190287920Abstract: A semiconductor package includes a semiconductor package substrate. An insulating layer is disposed on the semiconductor package substrate. A semiconductor chip is disposed on the semiconductor package substrate and is covered by the insulating layer. A reflective layer is disposed on the insulating layer and is spaced apart from the semiconductor chip. The reflective layer is configured to selectively transmit radiation through to the insulating layer. A protective layer is disposed on the reflective layer.Type: ApplicationFiled: November 27, 2018Publication date: September 19, 2019Inventors: KUN SIL LEE, DONG KWAN KIM, BO RAM KANG, HO GEON SONG, WON KEUN KIM
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Publication number: 20190139921Abstract: A semiconductor device includes a substrate, a contact pad arranged in the substrate, a bump arranged on the contact pad to be electrically connected with the contact pad, an insulating film arranged on the substrate to surround a side surface of the bump and to expose at least a portion of the contact pad to the bump, and a photosensitive film which is formed on the insulating film and comprises a polyimide, wherein the photosensitive film comprises a first region surrounding the side surface of the bump and having a first thickness measured in a vertical direction, and a second region arranged on the first region and having a second thickness thickermeasured in the vertical direction, wherein the second region is spaced apart from the bump in a horizontal direction, and wherein the second thickness is greater than a thickness two times thicker than a difference value between the second thickness and the first thickness.Type: ApplicationFiled: July 9, 2018Publication date: May 9, 2019Inventors: Nam Gyu BAEK, In Young LEE, Hyun Soo CHUNG, Ho Geon SONG
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Patent number: 9941196Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.Type: GrantFiled: April 15, 2016Date of Patent: April 10, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ho-Jin Lee, Tae-Je Cho, Dong-Hyeon Jang, Ho-Geon Song, Se-Young Jeong, Un-Byoung Kang, Min-Seung Yoon
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Publication number: 20160233155Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.Type: ApplicationFiled: April 15, 2016Publication date: August 11, 2016Inventors: Ho-Jin LEE, Tae-Je CHO, Dong-Hyeon JANG, Ho-Geon SONG, Se-Young JEONG, Un-Byoung KANG, Min-Seung YOON
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Patent number: 9343361Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.Type: GrantFiled: November 5, 2013Date of Patent: May 17, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ho-Jin Lee, Tae-Je Cho, Dong-Hyeon Jang, Ho-Geon Song, Se-Young Jeong, Un-Byoung Kang, Min-Seung Yoon
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Patent number: 9184065Abstract: A method of molding a semiconductor package includes coating liquid molding resin or disposing solid molding resin on a top surface of a semiconductor chip arranged on a substrate. The solid molding resin may include powdered molding resin or sheet-type molding resin. In a case where liquid molding resin is coated on the top surface of the semiconductor chip, the substrate is mounted between a lower molding and an upper molding, and then melted molding resin is filled in a space between the lower molding and the upper molding. In a case where the solid molding resin is disposed on the top surface of the semiconductor chip, the substrate is mounted on a lower mold and then the solid molding resin is heated and melts into liquid molding resin having flowability. An upper mold is mounted on the lower mold, and melted molding resin is filled in a space between the lower molding and the upper molding.Type: GrantFiled: January 6, 2015Date of Patent: November 10, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-young Ko, Jae-yong Park, Heui-seog Kim, Ho-geon Song
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Patent number: 9159680Abstract: A method of fabricating a semiconductor device includes preparing a semiconductor substrate having a circuit unit on an upper surface thereof, a metal pad electrically connected to the circuit unit, and a passivation layer that covers the circuit unit and exposes the metal pad, forming a first re-wiring layer that is electrically connected to the metal pad and is formed by a printing method to extend from the metal pad on the passivation layer and forming a second re-wiring layer on the first re-wiring layer using the first re-wiring layer as a seed by using an electro-plating process.Type: GrantFiled: June 1, 2012Date of Patent: October 13, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Wook Park, Kwang-Yong Lee, Ho-Geon Song
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Patent number: 9136260Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.Type: GrantFiled: December 2, 2013Date of Patent: September 15, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-seok Ahn, Dong-hyeon Jang, Ho-geon Song, Sung-jun Im, Chang-seong Jeon, Teak-hoon Lee, Sang-sick Park
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Patent number: 9099460Abstract: To manufacture a stack semiconductor package, a board mold covers a first semiconductor. The board mold includes a first face and a second face opposite to the first face. An active surface of the first semiconductor faces the second face. A first opening is formed in the board mold from the second surface. The first opening is disposed on the first semiconductor. A second opening penetrates the board mold from the first surface. A conductive metal layer fills the first and the second openings using an electroless plating method. A plurality of semiconductor devices is stacked on the first face of the board mold.Type: GrantFiled: August 22, 2014Date of Patent: August 4, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Yun-Rae Cho, Tae-Hoon Kim, Ho-Geon Song, Seok-Won Lee
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Publication number: 20150118798Abstract: A method of molding a semiconductor package includes coating liquid molding resin or disposing solid molding resin on a top surface of a semiconductor chip arranged on a substrate. The solid molding resin may include powdered molding resin or sheet-type molding resin. In a case where liquid molding resin is coated on the top surface of the semiconductor chip, the substrate is mounted between a lower molding and an upper molding, and then melted molding resin is filled in a space between the lower molding and the upper molding. In a case where the solid molding resin is disposed on the top surface of the semiconductor chip, the substrate is mounted on a lower mold and then the solid molding resin is heated and melts into liquid molding resin having flowability. An upper mold is mounted on the lower mold, and melted molding resin is filled in a space between the lower molding and the upper molding.Type: ApplicationFiled: January 6, 2015Publication date: April 30, 2015Inventors: Jun-young Ko, Jae-yong Park, Heui-seog Kim, Ho-geon Song
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Patent number: 8956921Abstract: A method of molding a semiconductor package includes coating liquid molding resin or disposing solid molding resin on a top surface of a semiconductor chip arranged on a substrate. The solid molding resin may include powdered molding resin or sheet-type molding resin. In a case where liquid molding resin is coated on the top surface of the semiconductor chip, the substrate is mounted between a lower molding and an upper molding, and then melted molding resin is filled in a space between the lower molding and the upper molding. In a case where the solid molding resin is disposed on the top surface of the semiconductor chip, the substrate is mounted on a lower mold and then the solid molding resin is heated and melts into liquid molding resin having flowability. An upper mold is mounted on the lower mold, and melted molding resin is filled in a space between the lower molding and the upper molding.Type: GrantFiled: March 15, 2013Date of Patent: February 17, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-young Ko, Jae-yong Park, Heui-seog Kim, Ho-geon Song
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Patent number: 8927340Abstract: Provided are a double-sided adhesive tape, semiconductor packages, and methods of fabricating the packages. A method of fabricating semiconductor packages includes providing a double-sided adhesive tape on a top surface of a carrier, the double-sided adhesive tape including a first adhesive layer and a second adhesive layer stacked on the first adhesive layer, the first adhesive layer of the double-sided adhesive tape being in contact with the top surface of the carrier, adhering active surfaces of a plurality of semiconductor chips onto the second adhesive layer of the double-sided adhesive tape, separating the first adhesive layer from the second adhesive layer such that the second adhesive layer remains on the active surfaces of the semiconductor chips, patterning the second adhesive layer to form first openings that selectively expose the active surfaces of the semiconductor chips, and forming first conductive components on the second adhesive layer to fill the first openings.Type: GrantFiled: February 21, 2013Date of Patent: January 6, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Woo Park, Seok-Hyun Lee, Ho-Geon Song
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Publication number: 20140363923Abstract: To manufacture a stack semiconductor package, a board mold covers a first semiconductor. The board mold includes a first face and a second face opposite to the first face. An active surface of the first semiconductor faces the second face. A first opening is formed in the board mold from the second surface. The first opening is disposed on the first semiconductor. A second opening penetrates the board mold from the first surface. A conductive metal layer fills the first and the second openings using an electroless plating method. A plurality of semiconductor devices is stacked on the first face of the board mold.Type: ApplicationFiled: August 22, 2014Publication date: December 11, 2014Inventors: Yun-Rae Cho, Tae-Hoon Kim, Ho-Geon Song, Seok-Won Lee
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Patent number: 8890294Abstract: To manufacture a stack semiconductor package, a board mold covers a first semiconductor. The board mold includes a first face and a second face opposite to the first face. An active surface of the first semiconductor faces the second face. A first opening is formed in the board mold from the second surface. The first opening is disposed on the first semiconductor. A second opening penetrates the board mold from the first surface. A conductive metal layer fills the first and the second openings using an electroless plating method. A plurality of semiconductor devices is stacked on the first face of the board mold.Type: GrantFiled: February 20, 2013Date of Patent: November 18, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Yun-Rae Cho, Tae-Hoon Kim, Ho-Geon Song, Seok-Won Lee
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Publication number: 20140196280Abstract: A method and apparatus to manufacture a flip chip package includes dotting a flux on a first preliminary bump of a package substrate, attaching a preliminary bump of a first semiconductor chip to the first preliminary bump of the package substrate via the flux, dotting a flux on a second preliminary bump of the package substrate, and attaching a preliminary bump of a second semiconductor chip to the second preliminary bump of the package substrate via the flux. Accordingly, an evaporation of the flux on the preliminary bump of the package substrate may be suppressed.Type: ApplicationFiled: March 18, 2014Publication date: July 17, 2014Applicant: Samsung Electronics Co., LtdInventors: Chang-Seong JEON, Ho-Geon SONG, Mitsuo UMEMOTO, Sang-Sick PARK