Patents by Inventor Hoi-Sung Chung
Hoi-Sung Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220415905Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.Type: ApplicationFiled: September 2, 2022Publication date: December 29, 2022Inventors: Jin-Bum KIM, Myung-Gil KANG, Kang-Hun MOON, Cho-Eun LEE, Su-Jin JUNG, Min-Hee CHOI, Yang XU, Dong-Suk SHIN, Kwan-Heum LEE, Hoi-Sung CHUNG
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Patent number: 11469237Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.Type: GrantFiled: April 18, 2019Date of Patent: October 11, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Bum Kim, Myung-Gil Kang, Kang-Hun Moon, Cho-Eun Lee, Su-Jin Jung, Min-Hee Choi, Yang Xu, Dong-Suk Shin, Kwan-Heum Lee, Hoi-Sung Chung
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Publication number: 20220102625Abstract: Phase change memory material stacks having a metal oxide liner for memory integrated circuits, related systems, and methods of fabrication are disclosed. Such phase change memory material stacks include a phase change material and a switching device and the sidewalls of the phase change memory material stacks are lined with a metal oxide to protect the material stacks during manufacture and use and to provide isolation between the material stacks.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Applicant: Intel CorporationInventors: Hari Chandrasekaran, Rajesh Venkatasubramanian, Hoi-Sung Chung
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Publication number: 20220102631Abstract: A semiconductor fabrication method, a semiconductor device and a semiconductor module. The method comprises: providing a stack on a substrate, the stack including a plurality of device layers comprising electrically conductive layers; patterning the stack using an etch to form trenches extending therethrough and pillars between the trenches; providing an a-Si-containing liner on sidewalls of the pillars; filling spaces between the pillars with one or more materials; and electrically coupling contact lines to the electrically conductive layers to form the semiconductor device. The a-Si-containing liner may include a liner made substantially of amorphous silicon, or a liner including a non-uniform distribution of a-Si and silicon nitride.Type: ApplicationFiled: September 26, 2020Publication date: March 31, 2022Inventors: Hoi-Sung Chung, Hari Chandrasekaran, Errol Todd Ryan
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Patent number: 11037991Abstract: A variable resistance memory device includes memory cells arranged on a substrate and an insulating structure between the memory cells. Each of the memory cells includes a variable resistance pattern and a switching pattern vertically stacked on the substrate. The insulating structure includes a first insulating pattern between the memory cells, and a second insulating pattern between the first insulating pattern and each of the memory cells. The first insulating pattern includes a material different from a material of the second insulating pattern.Type: GrantFiled: April 23, 2019Date of Patent: June 15, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoongoo Kang, Changwoo Seo, Dain Lee, Wook-Yeol Yi, Hoi Sung Chung
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Patent number: 10892263Abstract: Methods of fabricating a semiconductor device are provided. The methods may include forming a gate structure on a core-peri region of a substrate. The substrate may further include a cell region. The methods may also include forming a gate spacer on a sidewall of the gate structure, forming a first impurity region adjacent the gate spacer in the core-peri region of the substrate by performing a first ion implantation process, removing the gate spacer, forming a second impurity region in the core-peri region of the substrate between the gate structure and the first impurity region by performing a second ion implantation process, forming a stress film on the gate structure, an upper surface of the first impurity region, and an upper surface of the second impurity region, and forming a recrystallization region by crystallizing the first impurity region and the second impurity region by performing an annealing process.Type: GrantFiled: February 8, 2019Date of Patent: January 12, 2021Inventors: Hoi Sung Chung, Tae Sung Kang, Dong Suk Shin, Kong Soo Lee, Jun-Won Lee
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Publication number: 20200105832Abstract: A variable resistance memory device includes memory cells arranged on a substrate and an insulating structure between the memory cells. Each of the memory cells includes a variable resistance pattern and a switching pattern vertically stacked on the substrate. The insulating structure includes a first insulating pattern between the memory cells, and a second insulating pattern between the first insulating pattern and each of the memory cells. The first insulating pattern includes a material different from a material of the second insulating pattern.Type: ApplicationFiled: April 23, 2019Publication date: April 2, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: YOONGOO KANG, CHANGWOO SEO, DAIN LEE, WOOK-YEOL YI, HOI SUNG CHUNG
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Publication number: 20190386008Abstract: Methods of fabricating a semiconductor device are provided. The methods may include forming a gate structure on a core-peri region of a substrate. The substrate may further include a cell region. The methods may also include forming a gate spacer on a sidewall of the gate structure, forming a first impurity region adjacent the gate spacer in the core-peri region of the substrate by performing a first ion implantation process, removing the gate spacer, forming a second impurity region in the core-peri region of the substrate between the gate structure and the first impurity region by performing a second ion implantation process, forming a stress film on the gate structure, an upper surface of the first impurity region, and an upper surface of the second impurity region, and forming a recrystallization region by crystallizing the first impurity region and the second impurity region by performing an annealing process.Type: ApplicationFiled: February 8, 2019Publication date: December 19, 2019Inventors: Hoi Sung Chung, Tae Sung Kang, Dong Suk Shin, Kong Soo Lee, Jun-Won Lee
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Publication number: 20190244963Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.Type: ApplicationFiled: April 18, 2019Publication date: August 8, 2019Inventors: Jin-Bum Kim, Myung-Gil Kang, Kang-Hun Moon, Cho-Eun Lee, Su-Jin Jung, Min-Hee Choi, Yang Xu, Dong-Suk Shin, Kwan-Heum Lee, Hoi-Sung Chung
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Patent number: 10297601Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.Type: GrantFiled: November 15, 2016Date of Patent: May 21, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Bum Kim, Myung-Gil Kang, Kang-Hun Moon, Cho-Eun Lee, Su-Jin Jung, Min-Hee Choi, Yang Xu, Dong-Suk Shin, Kwan-Heum Lee, Hoi-Sung Chung
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Patent number: 9985036Abstract: In a semiconductor device, a first active region has a first ?-shape, and the second active region has a second ?-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.Type: GrantFiled: October 12, 2016Date of Patent: May 29, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Suk Shin, Myung-Sun Kim, Seong-Jin Nam, Pan-Kwi Park, Hoi-Sung Chung, Nae-In Lee
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Patent number: 9768300Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.Type: GrantFiled: January 13, 2017Date of Patent: September 19, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Suk Shin, Hyun-Chul Kang, Dong-Hyun Roh, Pan-Kwi Park, Geo-Myung Shin, Nae-In Lee, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim
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Patent number: 9741855Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.Type: GrantFiled: December 29, 2016Date of Patent: August 22, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Suk Shin, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim, Nae-In Lee
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Publication number: 20170186869Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.Type: ApplicationFiled: January 13, 2017Publication date: June 29, 2017Inventors: Dong-Suk SHIN, Hyun-Chul KANG, Dong-Hyun ROH, Pan-Kwi PARK, Geo-Myung SHIN, Nae-In LEE, Chul-Woong LEE, Hoi-Sung CHUNG, Young-Tak KIM
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Publication number: 20170148797Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.Type: ApplicationFiled: November 15, 2016Publication date: May 25, 2017Inventors: Jin-Bum KIM, Myung-Gil KANG, Kang-Hun MOON, Cho-Eun LEE, Su-Jin JUNG, Min-Hee CHOI, Yang XU, Dong-Suk SHIN, Kwan-Heum LEE, Hoi-Sung CHUNG
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Patent number: 9640658Abstract: A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate.Type: GrantFiled: October 28, 2015Date of Patent: May 2, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Dong Hyuk Kim, Dongsuk Shin, Myungsun Kim, Hoi Sung Chung
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Publication number: 20170110581Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.Type: ApplicationFiled: December 29, 2016Publication date: April 20, 2017Inventors: Dong-Suk SHIN, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim, Nae-In Lee
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Publication number: 20170033114Abstract: In a semiconductor device, a first active region has a first ?-shape, and the second active region has a second ?-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.Type: ApplicationFiled: October 12, 2016Publication date: February 2, 2017Inventors: Dong-Suk Shin, Myung-Sun Kim, Seong-Jin Nam, Pan-Kwi Park, Hoi-Sung Chung, Nae-In Lee
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Patent number: 9548301Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.Type: GrantFiled: January 28, 2016Date of Patent: January 17, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Suk Shin, Hyun-Chul Kang, Dong-Hyun Roh, Pan-Kwi Park, Geo-Myung Shin, Nae-In Lee, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim
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Patent number: 9537009Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.Type: GrantFiled: December 1, 2015Date of Patent: January 3, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Suk Shin, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim, Nae-In Lee