Patents by Inventor Hong Beom Pyeon
Hong Beom Pyeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948629Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.Type: GrantFiled: February 14, 2023Date of Patent: April 2, 2024Assignee: Mosaid Technologies IncorporatedInventors: HakJune Oh, Hong Beom Pyeon, Jin-Ki Kim
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Publication number: 20230253036Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.Type: ApplicationFiled: February 14, 2023Publication date: August 10, 2023Inventors: HakJune OH, Hong Beom PYEON, Jin-Ki KIM
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Patent number: 11600323Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.Type: GrantFiled: April 30, 2021Date of Patent: March 7, 2023Assignee: Mosaid Technologies IncorporatedInventors: HakJune Oh, Hong Beom Pyeon, Jin-Ki Kim
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Publication number: 20210327503Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.Type: ApplicationFiled: April 30, 2021Publication date: October 21, 2021Inventors: HakJune OH, Hong Beom PYEON, Jin-Ki KIM
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Patent number: 11017849Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.Type: GrantFiled: May 5, 2020Date of Patent: May 25, 2021Assignee: Conversant Intellectual Property Management Inc.Inventors: HakJune Oh, Hong Beom Pyeon, Jin-Ki Kim
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Publication number: 20200365202Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.Type: ApplicationFiled: May 5, 2020Publication date: November 19, 2020Inventors: HakJune OH, Hong Beom PYEON, Jin-Ki KIM
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Patent number: 10679695Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.Type: GrantFiled: January 16, 2019Date of Patent: June 9, 2020Inventors: HakJune Oh, Hong Beom Pyeon, Jin-Ki Kim
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Publication number: 20190214077Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.Type: ApplicationFiled: January 16, 2019Publication date: July 11, 2019Inventors: HakJune OH, Hong Beom PYEON, Jin-Ki KIM
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Patent number: 10223003Abstract: An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.Type: GrantFiled: November 9, 2017Date of Patent: March 5, 2019Assignee: Conversant Intellectual Property Management Inc.Inventors: Jin-Ki Kim, Hong Beom Pyeon
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Patent number: 10224098Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.Type: GrantFiled: March 28, 2018Date of Patent: March 5, 2019Assignee: Conversant Intellectual Property Management Inc.Inventors: HakJune Oh, Hong Beom Pyeon, Jin-Ki Kim
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Publication number: 20180261282Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.Type: ApplicationFiled: March 28, 2018Publication date: September 13, 2018Inventors: HakJune OH, Hong Beom PYEON, Jin-Ki KIM
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Patent number: 9977731Abstract: A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. The bridge device has memory organized as banks, where each bank is configured to have a virtual page size that is less than the maximum physical size of the page buffer. Therefore only a segment of data corresponding to the virtual page size stored in the page buffer is transferred to the bank. The virtual page size of the banks is provided in a virtual page size (VPS) configuration command having an ordered structure where the position of VPS data fields containing VPS configuration codes in the command correspond to different banks which are ordered from a least significant bank to a most significant bank. The VPS configuration command is variable in size, and includes only the VPS configuration codes for the highest significant bank being configured and the lower significant banks.Type: GrantFiled: September 16, 2013Date of Patent: May 22, 2018Assignee: Conversant Intellectual Property Management Inc.Inventors: Hong Beom Pyeon, Jin-Ki Kim, Peter B. Gillingham
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Publication number: 20180137912Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.Type: ApplicationFiled: January 11, 2018Publication date: May 17, 2018Inventors: HakJune OH, Hong Beom PYEON, Jin-Ki KIM
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Patent number: 9972381Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.Type: GrantFiled: January 11, 2018Date of Patent: May 15, 2018Assignee: Conversant Intellectual Property Management Inc.Inventors: HakJune Oh, Hong Beom Pyeon, Jin-Ki Kim
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Publication number: 20180129427Abstract: An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.Type: ApplicationFiled: November 9, 2017Publication date: May 10, 2018Inventors: Jin-Ki KIM, Hong Beom PYEON
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Patent number: 9966133Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.Type: GrantFiled: August 31, 2017Date of Patent: May 8, 2018Assignee: Conversant Intellectual Property Management Inc.Inventors: HakJune Oh, Hong Beom Pyeon, Jin-Ki Kim
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Publication number: 20170365333Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.Type: ApplicationFiled: August 31, 2017Publication date: December 21, 2017Inventors: HakJune OH, Hong Beom PYEON, Jin-Ki KIM
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Patent number: 9836391Abstract: Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.Type: GrantFiled: August 12, 2014Date of Patent: December 5, 2017Assignee: Conversant Intellectual Property Management Inc.Inventors: Hong Beom Pyeon, Jin-Ki Kim, HakJune Oh
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Patent number: 9836227Abstract: An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.Type: GrantFiled: September 22, 2016Date of Patent: December 5, 2017Assignee: Conversant Intellectual Property Management Inc.Inventors: Jin-Ki Kim, Hong Beom Pyeon
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Patent number: 9779804Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.Type: GrantFiled: November 8, 2016Date of Patent: October 3, 2017Assignee: Conversant Intellectual Property Management Inc.Inventors: HakJune Oh, Hong Beom Pyeon, Jin-Ki Kim