Abstract: Semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a semiconductor device includes a first epitaxial layer and a second epitaxial layer formed on mesas of the semiconductor layer. The thicknesses and doping concentrations of the first and second epitaxial layers and the mesa are selected to achieve charge balance in operation. In another embodiment, the semiconductor body is lightly doped and the thicknesses and doping concentrations of the first and second epitaxial layers are selected to achieve charge balance in operation.

Abstract: A puzzle set with a plurality of puzzle pieces is provided. Each puzzle piece has at least four puzzle piece sections. The puzzle piece sections comprise a shape that is square, hexagonal, octagonal, circular or any geometric shape. Also, the plurality of the puzzle pieces comprises different geometric shapes such as I-shaped, T-shaped, L-shaped, O-shaped, S-shaped, J-shaped, and Z-shaped. The plurality of the puzzle pieces are arranged against, connected to each other, or stack on each other to shape the pattern of the puzzle pattern and complete the puzzle.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area. The semiconductor power device further comprises a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches filled by a high density plasma (HDP) insulation layer. The semiconductor power device further comprises mesa areas of the semiconductor substrate disposed between the gate trenches wherein the mesa areas are recessed and having a top mesa surface disposed vertically below a top surface of the HDP insulation layer wherein the HDP insulation layer covering over the conductive gate material constituting a stick-out boundary-defining layer surrounding the recessed mesa areas in the active cell areas between the gate trenches.

Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

Abstract: Semiconductor devices are formed using a pair of thin epitaxial layers (nanotubes) of opposite conductivity type formed on sidewalls of dielectric-filled trenches. In one embodiment, a termination structure is formed in the termination area and includes a first termination cell formed in the termination area at an interface to the active area, the termination cell being formed in a mesa of the first semiconductor layer and having a first width; and an end termination cell being formed next to the first termination cell in the termination area, the end termination cell being formed in an end mesa of the first semiconductor layer and having a second width greater than the first width.

Abstract: In one aspect, the present invention relates to a mammalian cell-based high-throughput assay for the profiling and screening of human epithelial sodium channel (hENaC) cloned from a human kidney c-DNA library and is also expressed in other tissues including human taste tissue. The present invention further relates to amphibian oocyte-based medium-throughput electrophysiological assays for identifying human ENaC modulators, preferably ENaC enhancers. Compounds that modulate ENaC function in a cell-based ENaC assay are expected to affect salty taste in humans. The assays described herein have advantages over existing cellular expression systems. In the case of mammalian cells, such assays can be run in standard 96 or 384 well culture plates in high-throughput mode with enhanced assay results being achieved by the use of a compound that inhibits ENaC function, preferably an amiloride derivative such as Phenamil.

Abstract: The present invention discloses a content distribution method, system and a server. In one embodiment, the method includes: receiving a content distribution request form a client; obtaining all receiving ends designated by the content distribution request, and marking at least a portion of the receiving ends with a first status code; judging whether all the at least a portion of the receiving ends complete the distribution task, if not, controlling an internal distribution process until all the at least a portion of the receiving ends complete the distribution task.

Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

Abstract: This invention relates to electrophysiological assays that measure sodium conductance activity of a delta human epithelial sodium channel (ENaC) in the presence and absence of delta hENaC enhancers. Also, the invention generally relates to assays for identifying compounds that enhance the activity of delta hENaC, especially in an oocyte expression system. These compounds have potential application in modulating (enhancing) salty taste perception.

Abstract: A high density trench-gated MOSFET array and method are disclosed. It comprises semiconductor substrate partitioned into MOSFET array area and gate pickup area; epitaxial region, body region and source region; numerous precisely spaced active nitride-capped trench gate stacks (ANCTGS) embedded till the epitaxial region. Each ANCTGS comprises a stack of polysilicon trench gate with gate oxide shell and silicon nitride cap covering top of polysilicon trench gate and laterally registered to gate oxide shell. The ANCTGS forms, together with the source, body, epitaxial region, a MOSFET device in the MOSFET array area. Over MOSFET array area and gate pickup area, a patterned dielectric region atop the MOSFET array and a patterned metal layer atop the patterned dielectric region. Thus, the patterned metal layer forms, with the MOSFET array and the gate pickup area, self-aligned source and body contacts through the inter-ANCTGS separations.

Abstract: The present invention is concerned with a surface cleaning apparatus. The apparatus has substantially elongate and laterally extending head portion and a handle portion defining a longitudinal axis generally perpendicular to the head portion. The head portion includes opposite lateral ends, a first housing defining a first chamber and a rim forming an opening via which water from a surface to be cleaned enters the first chamber, a squeegee connected to the rim for directing the water via the opening to the first chamber, and guide means for guiding the water from the squeegee to the first chamber for initial containment, thus minimizing the water from dripping away from the apparatus in use, and the handle portion includes a second housing forming the handle portion and defining a second chamber for receiving and containing the water from the first chamber for subsequent containment.

Abstract: An implanting device is used for implanting a membrane in a biological tissue. The implanting device includes a sleeve, a membrane storage element, an injection element and a bubble generating element. The membrane storage element is fixed at the sleeve. The injection element is inserted in the sleeve and the membrane storage element, and includes a capturing end and connecting end. The capturing end is for capturing the membrane and has a hole. The bubble generating element is connected to the connecting end, and is for providing a gas that is then outputted via the hole. By the rotation of the injection element, the capturing end extends straight out of the membrane storage element or retracts straight into the membrane storage element.

Abstract: In one aspect, the present invention relates to a mammalian cell-based high-throughput assay for the profiling and screening of human epithelial sodium channel (hENaC) cloned from a human kidney c-DNA library and is also expressed in other tissues including human taste tissue. The present invention further relates to amphibian oocyte-based medium-throughput electrophysiological assays for identifying human ENaC modulators, preferably ENaC enhancers. Compounds that modulate ENaC function in a cell-based ENaC assay are expected to affect salty taste in humans. The assays described herein have advantages over existing cellular expression systems. In the case of mammalian cells, such assays can be run in standard 96 or 384 well culture plates in high-throughput mode with enhanced assay results being achieved by the use of a compound that inhibits ENaC function, preferably an amiloride derivative such as Phenamil.

Abstract: Semiconductor devices are formed using a pair of thin epitaxial layers (nanotubes) of opposite conductivity type formed on sidewalls of dielectric-filled trenches. In one embodiment, a termination structure is formed in the termination area and includes a first termination cell formed in the termination area at an interface to the active area, the termination cell being formed in a mesa of the first semiconductor layer and having a first width; and an end termination cell being formed next to the first termination cell in the termination area, the end termination cell being formed in an end mesa of the first semiconductor layer and having a second width greater than the first width.

Abstract: A reactive black dye composition is disclosed, which comprises: (A) a reactive blue dye represented by the following formula (I) or a salt thereof; and (B) a reactive red dye or a salt thereof, a reactive yellow dye or a salt thereof, or a combination thereof. Herein, R11, X1, X2, X31, X41 and n are defined in the specification. In addition, a method for dying fibers using the aforesaid reactive black dye composition is also disclosed.

Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

Abstract: Methods for forming a group III-V device structure are provided. A method includes forming a first through via structure penetrating through group III-V compound layers over a front surface of a semiconductor substrate. The method also includes thinning the semiconductor substrate from a back surface of the semiconductor substrate. The method further includes etching the semiconductor substrate from the back surface to form a via hole substantially aligned with the first through via structure. In addition, the method includes etching the semiconductor substrate from the back surface to form a recess extending from a bottom surface of the recess towards the first through via structure. The first through via structure is exposed by the via hole and the recess. The method also includes forming a conductive layer in the via hole and the recess to form a second through via structure connected to the first through via structure.

Abstract: Methods for forming a group III-V device structure are provided. A method includes forming a first through via structure penetrating through group III-V compound layers over a front surface of a semiconductor substrate. The method also includes thinning the semiconductor substrate from a back surface of the semiconductor substrate. The method further includes etching the semiconductor substrate from the back surface to form a via hole substantially aligned with the first through via structure. In addition, the method includes etching the semiconductor substrate from the back surface to form a recess extending from a bottom surface of the recess towards the first through via structure. The first through via structure is exposed by the via hole and the recess. The method also includes forming a conductive layer in the via hole and the recess to form a second through via structure connected to the first through via structure.

Abstract: A semiconductor device includes a substrate, overlaid by a III-V compound semiconductor layer. The substrate includes a circuit region and a seal ring region, wherein the seal ring region surrounds the circuit region. A seal ring structure is disposed in the seal ring region, wherein the seal ring structure includes a first via structure, extending through part of the substrate and the III-V compound semiconductor layer, that surrounds the circuit region.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area. The semiconductor power device further comprises a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches filled by a high density plasma (HDP) insulation layer. The semiconductor power device further comprises mesa areas of the semiconductor substrate disposed between the gate trenches wherein the mesa areas are recessed and having a top mesa surface disposed vertically below a top surface of the HDP insulation layer wherein the HDP insulation layer covering over the conductive gate material constituting a stick-out boundary-defining layer surrounding the recessed mesa areas in the active cell areas between the gate trenches.