Abstract: In certain aspects, a semiconductor device includes a substrate, a stack structure over the substrate and including interleaved conductive layers and dielectric layers, and a connection structure extending through the stack structure into the substrate. The connection structure includes a conductor layer and a spacer over a sidewall of the conductor layer. The conductor layer of the connection structure is in direct contact with the substrate.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers, a channel structure extending through the memory stack, and a through array contact (TAC) extending through the memory stack. Edges of the conductive layers along a sidewall of the TAC are recessed. The TAC includes a conductor layer and a spacer over the sidewall of the TAC.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A structure extending vertically through a memory stack including interleaved conductive layers and dielectric layers is formed above a substrate. A first dielectric layer is formed on the memory stack. An etch stop layer is formed on the first dielectric layer. A first contact is formed through the etch stop layer and the first dielectric layer and in contact with an upper end of the structure. A second dielectric layer is formed on the etch stop layer. A second contact is formed through the second dielectric layer and in contact with at least an upper end of the first contact.

Abstract: A method for forming a 3D memory device is disclosed. A gate electrode having an inverted “T” shape is formed above a substrate. A continuous blocking layer is formed on the gate electrode. A continuous charge trapping layer is formed on the blocking layer. A first thickness of a first part of the charge trapping layer extending laterally is greater than a second thickness of a second part of the charge trapping layer extending vertically. The second part of the charge trapping layer extending vertically is removed to form a plurality of discrete charge trapping layers disposed at different levels on the blocking layer from the first part of the charge trapping layer extending laterally. A continuous tunneling layer is formed on the discrete charge trapping layers. A continuous channel layer is formed on the tunneling layer.

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

Abstract: Embodiments of 3D memory devices are disclosed. In an example, a 3D memory device includes a memory stack, a structure penetrating the memory stack; a dielectric stack on the memory stack, and a contact structure penetrating the dielectric stack and being in contact with the structure. The dielectric stack comprises a first dielectric layer and a second dielectric layer having a first dielectric material, and an intermedia dielectric layer sandwiched by the first dielectric layer and the second dielectric layer, and having a second dielectric material different from the first dielectric material. The contact structure comprises a lower contact portion penetrating the first dielectric layer and the intermedia dielectric layer, the lower contact portion having a first lateral dimension, and an upper contact portion penetrating the second dielectric layer, the upper contact portion having a second lateral dimension less than the first lateral dimension.

Abstract: A micro-thrust and micro-impulse application device and method generates micro-thrust to a target by light pressure action from laser reflection. The device comprises a laser, a laser adjustment device, a beam splitter, a shutter, a reflector, and a laser power meter. Laser beam is generated by laser, adjusted by laser adjustment device, and divided into two paths by beam splitter. Laser in one path is measured at laser power meter; power measured determines magnitude for micro-thrust. In another path, it irradiates on the reflector on the target via shutter for generating micro-thrust. Light reflected by the reflector arrives at another laser power meter. Power of two laser paths are measured in real time by two laser power meters, acting micro-thrust is calculated by combining parameters including reflectivity and incident angle of laser irradiating the reflector, and light output power of the laser is adjusted in real time.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the second semiconductor structure and the third semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes a first array of memory cells. The third semiconductor structure includes a second array of memory cells. Each of the memory cells of the first and second arrays includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. The first array of memory cells is coupled to the peripheral circuit across the first bonding interface. The second array of memory cells is coupled to the peripheral circuit across the first bonding interface and the second bonding interfaces.

Abstract: In certain aspects, a memory device includes a memory cell including a vertical transistor, and a storage unit having a first end coupled to a first terminal of the vertical transistor. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body. The memory device also includes a metal bit line coupled to a second terminal of the vertical transistor via an ohmic contact and extending in a second direction perpendicular to the first direction. The memory device further includes a dielectric layer opposing the memory cell with the metal bit line positioned between the dielectric layer and the memory cell. The memory device further includes a conductor extending from the dielectric layer to couple to a second end of the storage unit.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells, and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. The vertical transistor includes a semiconductor body extending in the first direction, and a gate structure in contact with a plurality of sides of the semiconductor body. One end of the semiconductor body coupled to the storage unit is flush with the gate structure.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells, a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction, and a plurality of word lines coupled to the memory cells and each extending in a third direction perpendicular to the first direction and the second direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor.

Abstract: In certain aspects, a memory device includes a semiconductor layer, a peripheral circuit including a peripheral transistor in contact with the semiconductor layer, an array of memory cells disposed beside the semiconductor layer and the peripheral circuit, and bit lines coupled to the memory cells. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. Each of the bit lines extends in a second direction perpendicular to the first direction. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a first bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction. The array of memory cells is coupled to the peripheral circuit across the first bonding interface.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction. Two adjacent vertical transistors of the vertical transistors in the second direction are mirror-symmetric to one another. The array of memory cells is coupled to the peripheral circuit across the bonding interface.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. The vertical transistor includes a semiconductor body extending in the first direction, and a gate structure in contact with two opposite sides of the semiconductor body in the second direction. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction.

Abstract: Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate comprising a plurality of conductor/dielectric layer pairs, a channel structure extending vertically through the conductor/dielectric layer pairs in the memory stack, a TAC extending vertically through the conductor/dielectric layer pairs in the memory stack, and a dummy channel structure filled with a dielectric layer and extending vertically through the conductor/dielectric layer pairs in the memory stack.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, and a memory string extending vertically through the memory stack. The memory string includes a single crystalline silicon plug in a lower portion of the memory string, a memory film above the single crystalline silicon plug and along a sidewall of the memory string, and a single crystalline silicon channel over the memory film and along the sidewall of the memory string.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, a structure extending vertically through the memory stack, a first dielectric layer on the memory stack, an etch stop layer on the first dielectric layer, a second dielectric layer on the etch stop layer, a first contact through the etch stop layer and the first dielectric layer and in contact with an upper end of the structure, and a second contact through the second dielectric layer and in contact with at least an upper end of the first contact.

Abstract: The present invention relates to a semiconductor structure and method of forming the same. The semiconductor structure includes a first substrate and a first bonding layer on a surface of the first substrate, and the material of first bonding layer includes dielectric materials of silicon, nitrogen and carbon, and an atomic concentration of carbon in the first bonding layer gradually increases along with an increase of thickness of the first bonding layer from the surface of first substrate and reaches a maximum atomic concentration of carbon at a surface of the first bonding layer.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a substrate, an alternating layer stack on the substrate, and a barrier structure extending vertically through the alternating layer stack. The alternating layer stack includes (i) an alternating dielectric stack having a plurality of dielectric layer pairs enclosed laterally by at least the barrier structure, and (ii) an alternating conductor/dielectric stack having a plurality of conductor/dielectric layer pairs. The 3D memory device also includes a channel structure and a source structure each extending vertically through the alternating conductor/dielectric stack, and a contact structure extending vertically through the alternating dielectric stack. The source structure includes at least one staggered portion along a respective sidewall.